Microelectromechanical pressure sensor including reference capacitor

• US 10,065,851 B2
• Filed: 09/20/2011
• Issued: 09/04/2018
• Est. Priority Date: 09/20/2010
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Bryzek, Janusz
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): NGUYEN, LAWRENCE-LIN T
• Application Number:
  US13/821,598
• Publication Number:
  US 20130277772A1
• Time in Patent Office: 2,541 Days
• CPC Class Codes: B81B 2201/0257 Microphones or microspeakers
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81B 3/0021 Transducers for transforming electrical into mechanical energy or vice versa dynamo-electric machines H02K99/00; electrostatic machines H02N1/00; piezoelectric devices H10N30/00
• CPC Class Codes: B81C 1/00015 for manufacturing microsystems
• CPC Class Codes: B81C 1/00158 Diaphragms, membranes manufacture process for semi-permeable inorganic membranes B01D67/0039
• CPC Class Codes: G01L 19/04 Means for compensating for effects of changes of temperature , i.e. other than electric compensation
• CPC Class Codes: G01L 9/0016 of a diaphragm
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm

Abstract

This document discusses, among other things, an apparatus including a silicon die including a vibratory diaphragm, the die having a silicon die top opposite a silicon die bottom, with a top silicon die port extending from the silicon die top through the silicon die to a top of the vibratory diaphragm, and with a bottom silicon die port extending from the silicon die bottom to a bottom of the vibratory diaphragm, wherein the bottom silicon die port has a cross sectional area that is larger than a cross-sectional area of the top silicon die port, a capacitor electrode disposed along a bottom of the silicon die, across the bottom silicon die port, the capacitor electrode including a first signal generation portion that is coextensive with the top silicon die port, and a second signal generation portion surrounding the first portion.

Claims

1. An apparatus comprising:

a silicon die including a vibratory diaphragm, the silicon die having a silicon die top opposite a silicon die bottom, with a top silicon die port extending from the silicon die top through the silicon die to a top of the vibratory diaphragm, and with a bottom silicon die port extending from the silicon die bottom to a bottom of the vibratory diaphragm, wherein the bottom silicon die port has a cross sectional area that is larger than a cross-sectional area of the top silicon die port;

a capacitor electrode layer disposed along a bottom of the silicon die and across the bottom silicon die port, the capacitor electrode layer including;

a first electrode included in a first micro-electromechanical (MEMs) capacitor, the first electrode being coextensive with the top silicon die port; and

a second electrode included in a second MEMs capacitor, the second electrode being coplanar with and surrounding the first electrode.

2. The apparatus of claim 1, wherein the capacitor electrode layer is a layer that defines a cavity including the bottom silicon die port.

3. The apparatus of claim 2, wherein the cavity is configured to be sealed under vacuum relative to an atmosphere to which the vibratory diaphragm is exposed.

4. The apparatus of claim 1, wherein the silicon die is comprised of a bottom portion including the vibratory diaphragm, and a top portion joined to the bottom portion.

5. The apparatus of claim 1, wherein a capacitance of the first MEMs capacitor is greater than a capacitance of the second MEMs capacitor.

6. The apparatus of claim 5, wherein a capacitance of the first MEMS capacitor is 1000 times greater than a capacitance of the second MEMs capacitor.

13. The apparatus of claim 1, comprising a differential circuit coupled to the first electrode and the second electrode and configured to measure a signal difference between the first electrode and the second electrode to provide a capacitance differential signal.

7. An apparatus comprising:

a silicon die including a vibratory diaphragm, the silicon die having a silicon die top opposite a silicon die bottom, with a top silicon die port extending from the silicon die top through the silicon die to a top of the vibratory diaphragm, and with a bottom silicon die port extending from the silicon die bottom to a bottom of the vibratory diaphragm, wherein the bottom silicon die port has a cross sectional area that is larger than a cross-sectional area of the top silicon die port; and

a capacitor electrode layer disposed along a bottom of the silicon die and across the bottom silicon die port, the capacitor electrode layer including;

a first electrode included in a first micro-electromechanical (MEMs) capacitor, the first electrode being coextensive with the top silicon die port; and

a second electrode included in a second MEMs capacitor, the second electrode being coplanar with and surrounding the first electrode, the capacitor electrode being disposed on a substrate, the substrate including an integrated circuit.

8. The apparatus of claim 7, wherein the substrate is encompassed at least partially by an overmold.

9. The apparatus of claim 8, wherein the silicon die is physically separated from the overmold.

10. The apparatus of claim 7, wherein the substrate includes at least one through-silicon-via physically and electrically coupled to the capacitor electrode layer.

11. The apparatus of claim 7, wherein the substrate includes a via wafer, wherein the via wafer is coupled to an integrated circuit wafer, wherein the integrated circuit wafer includes an application specific integrated circuit, wherein the via wafer is coupled to the integrated circuit wafer with solder bump interconnects.

12. The apparatus of claim 11, comprising a seal disposed between the via wafer and the integrated circuit wafer, outside the interconnects.

14. A method, comprising:

forming a top portion of a silicon die with a top silicon die port extending through to a vibratory membrane;

forming a bottom portion of the silicon die with vias extending through;

coupling the top portion of the silicon die to the bottom portion of the silicon die to define a cavity; and

forming a capacitor electrode layer onto a bottom of the coupled top portion of the silicon die and the bottom portion of the silicon die, the capacitor electrode layer extending over at least one via,

the forming the capacitor electrode layer including;

forming a first electrode included in a first micro-electromechanical (MEMs) capacitor, the first electrode being coextensive with the top silicon die port; and

forming a second electrode included in a second MEMs capacitor, the second electrode being coplanar with and extending around the first electrode.

15. The method of claim 14, wherein forming the bottom portion of the silicon die includes:

etching portions of a first wafer to include via openings;

growing an oxide on the etched portions of the first wafer;

depositing a film onto the grown oxide;

removing the film from a bottom side of the grown oxide;

removing the film from a top side of the grown oxide;

disposing a mask on the top side of the grown oxide;

after disposing the mask, buffered oxide etching the grown oxide;

after buffered oxide etching, dry etching via recesses;

after dry etching the via recesses, removing the mask; and

stripping the grown oxide to form the bottom portion of the silicon die.

16. The method of claim 14, wherein coupling the top portion of the silicon die to the bottom portion of the silicon die to define the cavity includes:

coupling the top portion of the silicon die, being a die from a silicon on insulator layer, to a via layer; and

coupling the top portion of the silicon die to the bottom portion of the silicon die to define a cavity between the top portion of the silicon die and the bottom portion of the silicon die.

17. The method of claim 14, wherein forming the capacitor electrode layer includes:

excising the bottom portion of the silicon die; and

growing dielectric on the excised bottom portion of the silicon die.

18. The method of claim 17, wherein forming the first electrode and forming the second electrode includes:

etching a pattern into the dielectric on the excised bottom portion of the silicon die; and

depositing a conductor into the pattern.

19. The method of claim 18, wherein etching the pattern into the dielectric on the excised bottom portion of the silicon die comprises breaking electrical communication between at least two vias disposed through the bottom portion of the silicon die.

20. The method of claim 14, wherein forming the top portion of the silicon die includes:

etching a top silicon port into the top portion of the silicon die; and

etching grown oxide from inside the top silicon port.