Testing holders for chip unit and die package
First Claim
Patent Images
1. A testing holder for a chip unit, comprising:
- a holder body configured to contain the chip unit; and
a pressure releasing device formed on the holder body configured to release an insertion pressure when the chip unit is inserted in the holder body.
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Abstract
A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
45 Citations
20 Claims
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1. A testing holder for a chip unit, comprising:
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a holder body configured to contain the chip unit; and a pressure releasing device formed on the holder body configured to release an insertion pressure when the chip unit is inserted in the holder body. - View Dependent Claims (2, 3, 4, 5)
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6. A multi site holding frame for a plurality of chip units, comprising:
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a first holder frame having a plurality of testing holders, each of the plurality of testing holders including a holder body configured to contain one of the plural chip units, wherein the holder frame comprises; a power supply, and a temperature controller; a multi site probe card, including plural contact probes and plural contactless coils; a second holder frame; plural frame guiding pins; and a multi site probe card having plural probing devices to probe one of a contact and a contactless transmission, wherein the holder body has an upper surrounding wall including a first and a second openings and a lower surrounding wall including a third opening, the upper surrounding wall and the lower surrounding wall are connected by plural guide pins, and the one of the chip units is insertable into the holder body via the first, the second, and the third openings. - View Dependent Claims (7, 8, 9, 10, 11, 12, 20)
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13. A method of testing a plurality of chip units, comprising:
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inserting a first chip unit into a testing holder and inserting a second chip unit into a second testing holder, wherein the first chip unit and the second chip unit have different dimensions, and the first testing holder and second testing holder have same outer dimensions; inserting the first testing holder and the second testing holder into a first open recess and a second open recess, respectively, of a holder frame; positioning a multi-site probe card having a plurality of probe contacts and a plurality of contactless coils over the holder frame; testing the first chip unit and the second chip unit to determine whether the first and second chip units are defective chip units; and using a temperature controller to control the temperature of the testing within a range of from about −
50°
C. to about 150°
C. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification