Dynamically controlling cache size to maximize energy efficiency

• US 10,067,553 B2
• Filed: 09/20/2016
• Issued: 09/04/2018
• Est. Priority Date: 10/31/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ananthakrishnan, Avinash N., Rotem, Efraim, Weissmann, Eliezer, Rajwan, Doron, Shulman, Nadav, Naveh, Alon, Abu-Salah, Hisham
• Primary Examiner(s): TSENG, CHENG YUAN
• Application Number:
  US15/270,208
• Publication Number:
  US 20170010656A1
• Time in Patent Office: 714 Days
• Field of Search: None
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/282 Partitioned cache
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a first core;

a second core;

a first cache memory coupled to the first core and the second core and to operate with a plurality of ways, the first cache memory comprising an N way set associative cache memory, wherein the first cache memory comprises a shared cache memory;

first hardware logic to cause one or more of the first core and the second core to transition from a first power state to a second power state, wherein the second power state comprises a package low power state in which the first core and the second core are power gated and at least one way of the first cache memory is to be powered with a retention voltage to maintain a context of at least one of the first core and the second core; and

second hardware logic to dynamically vary a size of the first cache memory based at least in part on a performance metric of a workload to be executed on at least one of the first core and the second core, wherein the second hardware logic is to cause a single first additional way of the N ways of the first cache memory to be enabled to increase a size of the first cache memory based on a comparison of a first value of the performance metric to a threshold.

2. The processor of claim 1, further comprising a second cache memory.

3. The processor of claim 2, wherein the second cache memory is included within the first core.

4. The processor of claim 1, further comprising a controller, the controller comprising at least one of the first hardware logic and the second hardware logic.

5. The processor of claim 1, further comprising at least one Peripheral Component Interconnect Express (PCIe) interface.

6. The processor of claim 1, wherein the second hardware logic is to cause a second additional way of the first cache memory to be enabled to increase the size of the first cache memory based on a comparison of a second value of the performance metric to the threshold.

7. The processor of claim 1, further comprising a third cache memory associated with the second core, wherein the second cache memory is associated with the first core.

8. A computing system comprising:

a processor;

memory coupled to the processor; and

storage coupled to the processor, wherein the processor comprises;

a first core;

a second core;

a first cache memory coupled to the first core and the second core and to operate with a plurality of ways, the first cache memory comprising an N way set associative cache memory;

first hardware logic to cause one or more of the first core and the second core to transition from a first power state to a second power state, wherein the second power state comprises a package low power state in which the first core and the second core are power gated and at least one way of the first cache memory is to be powered with a retention voltage to maintain a context of at least one of the first core and the second core; and

second hardware logic to dynamically vary a size of the first cache memory based at least in part on a performance metric of a workload to be executed on at least one of the first core and the second core, wherein the second hardware logic is to cause a single first additional way of the N ways of the first cache memory to be enabled to increase a size of the first cache memory based on a first result of a comparison of a first value of the performance metric to a threshold and cause a single second way of the N ways of the first cache memory to be disabled to decrease the size of the first cache memory based on a second result of the comparison of the first value of the performance metric to the threshold.

9. The computing system of claim 8, further comprising at least one communication device coupled to the processor.

10. The computing system of claim 8, wherein the computing system comprises a server.

11. At least one non-transitory computer readable storage medium comprising instructions that when executed enable a system to:

transition at least one of a first core and a second core of a multicore processor from a first power state to a second power state;

compare a first value of a performance metric of a workload executing on at least one of the first core and the second core to a threshold; and

dynamically vary a size of a first cache memory coupled to the first core and the second core based at least in part on a first result of a comparison of the first value to the threshold, including enabling a first additional way of the first cache memory to increase a size of the first cache memory, the first cache memory comprising an N way set associative cache memory and the second power state comprising a package low power state in which the first core and the second core are power gated and at least one way of the first cache memory is to be powered with a retention voltage to maintain a context state of at least one of the first core and the second core.

12. The at least one non-transitory computer readable medium of claim 11, further comprising instructions that when executed enable the system to:

compare a second value of the performance metric of the workload executing on the at least one of the first core and the second core to the threshold; and

enable a second additional way of the first cache memory to increase the size of the first cache memory based at least in part on a second result of the comparison of the second value to the threshold.

13. The at least one non-transitory computer readable medium of claim 11, further comprising instructions that when executed enable the system to enable all of a plurality of ways of the first cache memory based at least in part on another value of the performance metric of the workload.