Dynamically controlling cache size to maximize energy efficiency
First Claim
Patent Images
1. A processor comprising:
- a first core;
a second core;
a first cache memory coupled to the first core and the second core and to operate with a plurality of ways, the first cache memory comprising an N way set associative cache memory, wherein the first cache memory comprises a shared cache memory;
first hardware logic to cause one or more of the first core and the second core to transition from a first power state to a second power state, wherein the second power state comprises a package low power state in which the first core and the second core are power gated and at least one way of the first cache memory is to be powered with a retention voltage to maintain a context of at least one of the first core and the second core; and
second hardware logic to dynamically vary a size of the first cache memory based at least in part on a performance metric of a workload to be executed on at least one of the first core and the second core, wherein the second hardware logic is to cause a single first additional way of the N ways of the first cache memory to be enabled to increase a size of the first cache memory based on a comparison of a first value of the performance metric to a threshold.
0 Assignments
0 Petitions
Accused Products
Abstract
In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
-
Citations
13 Claims
-
1. A processor comprising:
-
a first core; a second core; a first cache memory coupled to the first core and the second core and to operate with a plurality of ways, the first cache memory comprising an N way set associative cache memory, wherein the first cache memory comprises a shared cache memory; first hardware logic to cause one or more of the first core and the second core to transition from a first power state to a second power state, wherein the second power state comprises a package low power state in which the first core and the second core are power gated and at least one way of the first cache memory is to be powered with a retention voltage to maintain a context of at least one of the first core and the second core; and second hardware logic to dynamically vary a size of the first cache memory based at least in part on a performance metric of a workload to be executed on at least one of the first core and the second core, wherein the second hardware logic is to cause a single first additional way of the N ways of the first cache memory to be enabled to increase a size of the first cache memory based on a comparison of a first value of the performance metric to a threshold. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A computing system comprising:
-
a processor; memory coupled to the processor; and storage coupled to the processor, wherein the processor comprises; a first core; a second core; a first cache memory coupled to the first core and the second core and to operate with a plurality of ways, the first cache memory comprising an N way set associative cache memory; first hardware logic to cause one or more of the first core and the second core to transition from a first power state to a second power state, wherein the second power state comprises a package low power state in which the first core and the second core are power gated and at least one way of the first cache memory is to be powered with a retention voltage to maintain a context of at least one of the first core and the second core; and second hardware logic to dynamically vary a size of the first cache memory based at least in part on a performance metric of a workload to be executed on at least one of the first core and the second core, wherein the second hardware logic is to cause a single first additional way of the N ways of the first cache memory to be enabled to increase a size of the first cache memory based on a first result of a comparison of a first value of the performance metric to a threshold and cause a single second way of the N ways of the first cache memory to be disabled to decrease the size of the first cache memory based on a second result of the comparison of the first value of the performance metric to the threshold. - View Dependent Claims (9, 10)
-
-
11. At least one non-transitory computer readable storage medium comprising instructions that when executed enable a system to:
-
transition at least one of a first core and a second core of a multicore processor from a first power state to a second power state; compare a first value of a performance metric of a workload executing on at least one of the first core and the second core to a threshold; and dynamically vary a size of a first cache memory coupled to the first core and the second core based at least in part on a first result of a comparison of the first value to the threshold, including enabling a first additional way of the first cache memory to increase a size of the first cache memory, the first cache memory comprising an N way set associative cache memory and the second power state comprising a package low power state in which the first core and the second core are power gated and at least one way of the first cache memory is to be powered with a retention voltage to maintain a context state of at least one of the first core and the second core. - View Dependent Claims (12, 13)
-
Specification