Memory activity driven adaptive performance measurement
First Claim
1. A memory controller comprising:
- a plurality of memory interfaces, each of the plurality of memory interfaces communicatively coupled to a respective memory module comprising at least one rank and at least one bank;
a profiler configured to maintain a record of respective memory accesses to each rank and to each bank of each memory module;
a control unit configured to adaptively select which portion of the respective memory modules coupled to the plurality of memory interfaces to monitor traffic access patterns for each of a plurality of sampling periods based on one of a track hotness mode or a track coldness mode as indicated by bits in a control register; and
a counter configured to count the respective number of memory accesses to the selected portion of the memory modules during the respective sampling period;
wherein the control unit is further configured to generate interrupts periodically to provide data from the counter to a processor for workload and usage data analysis;
wherein the control unit is further configured to analyze, using the workload and usage data analysis, how the memory modules behave when peak bandwidth workload is run and how the power management is handled when low workload bandwidth is run;
wherein when configured to adaptively select which portion of the respective memory modules to monitor based on the track hotness mode, the control unit is configured to retrieve data from the profiler regarding the number of memory accesses for each rank and to select, for monitoring in a next sampling period of the plurality of sampling periods, only the portion of the respective memory modules having the highest number of memory accesses during a given time window; and
wherein when configured to adaptively select which portion of the respective memory modules to monitor based on the track coldness mode, the control unit is configured to retrieve data from the profiler regarding the number of memory accesses for each rank and to select, for monitoring in a next sampling period of the plurality of sampling periods, only the portion of the respective memory modules having the lowest number of memory accesses during a given time window.
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Abstract
A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.
22 Citations
19 Claims
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1. A memory controller comprising:
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a plurality of memory interfaces, each of the plurality of memory interfaces communicatively coupled to a respective memory module comprising at least one rank and at least one bank; a profiler configured to maintain a record of respective memory accesses to each rank and to each bank of each memory module; a control unit configured to adaptively select which portion of the respective memory modules coupled to the plurality of memory interfaces to monitor traffic access patterns for each of a plurality of sampling periods based on one of a track hotness mode or a track coldness mode as indicated by bits in a control register; and a counter configured to count the respective number of memory accesses to the selected portion of the memory modules during the respective sampling period; wherein the control unit is further configured to generate interrupts periodically to provide data from the counter to a processor for workload and usage data analysis; wherein the control unit is further configured to analyze, using the workload and usage data analysis, how the memory modules behave when peak bandwidth workload is run and how the power management is handled when low workload bandwidth is run; wherein when configured to adaptively select which portion of the respective memory modules to monitor based on the track hotness mode, the control unit is configured to retrieve data from the profiler regarding the number of memory accesses for each rank and to select, for monitoring in a next sampling period of the plurality of sampling periods, only the portion of the respective memory modules having the highest number of memory accesses during a given time window; and wherein when configured to adaptively select which portion of the respective memory modules to monitor based on the track coldness mode, the control unit is configured to retrieve data from the profiler regarding the number of memory accesses for each rank and to select, for monitoring in a next sampling period of the plurality of sampling periods, only the portion of the respective memory modules having the lowest number of memory accesses during a given time window. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A memory sub-system comprising:
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a processor; a plurality of memory modules each comprising at least one rank and at least one bank; and a memory controller having a plurality of memory interfaces, each memory interface communicatively coupled to a respective one of the plurality of memory modules; wherein the memory controller further comprises a performance measurement component configured to maintain a record of respective memory accesses to each rank and to each bank of each memory module and to adaptively select which portion of the respective memory modules to monitor traffic access patterns for each of a plurality of sampling periods based on one of a track hotness mode or a track coldness mode as indicated by bits in a control register; wherein the performance measurement component is further configured to count the respective number of memory accesses to the selected portion of the memory modules during the respective sampling period and to generate interrupts periodically to provide the counted number of memory accesses to the processor for workload and usage data analysis; wherein the performance measurement component is further configured to analyze, using the workload and usage data analysis, how the memory modules behave when peak bandwidth workload is run and how the power management is handled when low workload bandwidth is run; wherein when configured to adaptively select which portion of the respective memory modules to monitor based on the track hotness mode, the performance measurement component is configured to select, for monitoring in a next sampling period of the plurality of sampling periods, only the portion of the respective memory modules having the highest number of memory accesses during a given time window; and wherein when configured to adaptively select which portion of the respective memory modules to monitor based on the track coldness mode, the performance measurement component is configured to select, for monitoring in a next sampling period of the plurality of sampling periods, only the portion of the respective memory modules having the lowest number of memory accesses during a given time window. - View Dependent Claims (15, 16, 17, 18, 19)
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Specification