Time-based on-chip hardware performance monitor

• US 10,067,847 B1
• Filed: 09/08/2015
• Issued: 09/04/2018
• Est. Priority Date: 09/08/2015
• Status: Active Grant

• Current Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Original Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Inventors: Habusha, Adi, Avron, Itai
• Primary Examiner(s): Tran, Long K
• Application Number:
  US14/848,139
• Time in Patent Office: 1,092 Days
• Field of Search: 702186, 324 7616, 324 7676, 324 7662
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 2201/88 Monitoring involving counting

Abstract

Disclosed herein is a performance monitor for a functional block of a system, the performance monitor comprising a counter circuit, wherein the counter circuit includes a programmable time window counter configured to determine an adjustable counting period, and an event counter coupled to the time window counter. The event counter is configured to count a number of occurrences of an event occurring in the functional block during the counting period, and record the number of occurrences of the event during the counting period and generate an output trigger signal when the number of occurrences of the event during the counting period is outside of a programmable threshold band, or after receiving an input trigger signal from a cross trigger network triggered by other performance monitors in electrical communication with the cross trigger network.

Claims

1. A hardware performance monitor for a functional block of a system, comprising:

a counter circuit, wherein the counter circuit includes;

an event select multiplexer configured to select an event occurring in the functional block, the event being a type of activities occurring in the functional block;

a time window counter with a programmable maximum counter value, the maximum counter value determining a counting period, wherein the time window counter restarts at zero after the maximum counter value is reached;

an event counter coupled to the event select multiplexer and the time window counter, wherein the event counter is configured to;

count a number of occurrences of the selected event occurring in the functional block during the counting period;

restart counting the selected event in a new counting period if the number of occurrences of the selected event during the counting period falls within a threshold band; and

generate an output trigger signal when the number of occurrences of the selected event during the counting period falls outside of the threshold band; and

an interface with a cross trigger network,

wherein the event counter sends the output trigger signal to the cross trigger network and receives an input trigger signal from the cross trigger network through the interface; and

wherein the event counter is configurable to pause counting after receiving the input trigger signal.

2. The hardware performance monitor of claim 1, wherein the event counter is configured to generate an interrupt signal or an overflow trigger signal when an overflow of the event counter occurs, and wherein the overflow trigger signal is sent to the cross trigger network through the interface.

3. The hardware performance monitor of claim 1, wherein the programmable maximum counter value of the time window counter is dynamically programmable such that the counting period of the event counter can be adjusted dynamically to different values.

4. The hardware performance monitor of claim 1,

wherein the hardware performance monitor is configured to interact with another hardware performance monitor in the system through the cross trigger network;

and

wherein the output trigger signal from the hardware performance monitor is converted to a global input trigger signal by the cross trigger network, and sent to the other hardware performance monitor to trigger recording of a counter value of the other hardware performance monitor.

5. The hardware performance monitor of claim 1, wherein the hardware performance monitor is configured to record the number of occurrences of the selected event during the counting period when the number of occurrences of the selected event during the counting period falls outside of the threshold band or after the event counter receives the input trigger signal.

6. A performance monitor for a functional block of a system, the performance monitor comprising:

a counter circuit, wherein the counter circuit includes;

a programmable time window counter configured to determine an adjustable counting period; and

an event counter coupled to the time window counter, wherein the event counter is configured to;

count a number of occurrences of an event occurring in the functional block during the counting period, the event being a type of activities occurring in the functional block; and

record the number of occurrences of the event during the counting period when the number of occurrences of the event during the counting period is outside of a threshold band, wherein the threshold band includes at least one of a low threshold or a high threshold; and

wherein the event counter is further configured to;

receive an input trigger signal; and

in response to receiving the input trigger signal, record the number of occurrences of the event occurring in the functional block during the counting period.

7. The performance monitor of claim 6, wherein the threshold band is programmable.

8. The performance monitor of claim 6, wherein the event counter is further configured to record a number of occurrences of the event during each counting period of a plurality of counting periods around the counting period during which the number of occurrences of the event is outside of the threshold band or around the counting period during which the trigger signal is received.

9. The performance monitor of claim 6, further comprising a trigger interface, the trigger interface including an output trigger port and an input trigger port,

wherein the performance monitor is configured to transmit an output trigger signal through the output trigger port when the number of occurrences of the event during the counting period is outside of a threshold band;

and

wherein the event counter is configured to receive the input trigger signal through the input trigger port.

10. The performance monitor of claim 6, wherein the performance monitor is configured to generate an output trigger signal when a number of occurrences of the event during each of two or more consecutive counting periods is outside of a threshold band.

11. The performance monitor of claim 6, wherein a maximum counter value of the time window counter is dynamically reconfigurable such that the counting period can be adjusted dynamically for different counting resolutions.

12. The performance monitor of claim 6, wherein the event counter is configured to generate a trace trigger signal or increase a counter value of the event counter after a programmable number of events.

13. The performance monitor of claim 6, wherein the counter circuit is configured to repeatedly count the event until the number of occurrences of the event in a first counting period is outside of a threshold band, and to record a number of counting periods that have passed before the first counting period.

14. The performance monitor of claim 6, further comprising:

a plurality of counter circuits, each counter circuit of the plurality of counter circuits including a respective event counter,

wherein the performance monitor is configured to generate an output trigger signal when a number of occurrences of an event being counted during a counting period is outside of a threshold band in each of two or more event counters.