Apparatus and method for low-overhead synchronous page table updates

• US 10,067,870 B2
• Filed: 04/01/2016
• Issued: 09/04/2018
• Est. Priority Date: 04/01/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Doshi, Kshitij A., Hughes, Christopher J.
• Primary Examiner(s): Giardino, Jr., Mark
• Application Number:
  US15/088,985
• Publication Number:
  US 20170286300A1
• Time in Patent Office: 886 Days
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2212/65 Details of virtual memory and virtual address translation
• CPC Class Codes: G06F 2212/68 Details of translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/682 Multiprocessor TLB consistency

Abstract

An apparatus and method are described for low overhead synchronous page table updates. For example, one embodiment of a processor comprises: a set of one or more cores to execute instructions and process data; a translation lookaside buffer (TLB) comprising a plurality of entries to cache virtual-to-physical address translations usable by the set of one or more cores when executing the instructions; locking circuitry to allow a thread to lock a first page table entry (PTE) in the TLB to ensure that only one thread can modify the first PTE at a time, wherein the TLB is to modify the first PTE upon the thread acquiring the lock; a PTE invalidation circuit to execute a PTE invalidate instruction on a first core to invalidate the first PTE in other TLBs of other cores, the PTE invalidation circuit, responsive to execution of the PTE invalidate instruction, to responsively determine a number of other TLBs of other cores which need to be notified of the PTE invalidation, transmit PTE invalidate messages to the other TLBs, and wait for responses; and the locking circuitry to release the lock on the first PTE responsive to receiving responses from all of the other TLBs.

Claims

1. A processor comprising:

a plurality of cores to execute instructions and process data;

one or more translation lookaside buffers (TLBs) comprising a plurality of entries to cache virtual-to-physical address translations usable by at least one of the plurality of cores when executing the instructions;

a page table entry (PTE) invalidation circuit to execute a PTE invalidate instruction on a first core to invalidate a first PTE in TLBs of other cores, the PTE invalidation circuit, responsive to execution of the PTE invalidate instruction, to responsively determine a number of other TLBs of other cores which need to be notified of the PTE invalidation, transmit PTE invalidate messages to the other TLBs, and wait for responses;

locking circuitry to allow a thread to lock the first PTE in the first TLB to ensure that only one thread can modify the first PTE at a time; and

an invalidation PTE state machine circuit to be programmed with a count value initially set to the number of other TLBs which need to be notified, the invalidation PTE state machine circuit to decrement the count value upon receiving each response from each of the other TLBs, the locking circuitry to release the lock when the count value has been decremented to a threshold value.

2. The processor as in claim 1

wherein the first TLB is to modify the first PTE upon the thread acquiring the lock;

and

the locking circuitry to release the lock on the first PTE responsive to receiving responses from all of the other TLBs.

3. The processor as in claim 2 wherein the locking circuitry is to implement a mutex operation to acquire the lock on the first PTE.

4. The processor as in claim 2 wherein each TLB comprises PTE invalidate request handling circuitry to receive invalidation requests transmitted from other TLBs, the invalidate request handling circuitry to responsively cause the TLBs to invalidate one or more PTEs identified in the invalidation requests and transmit a response indicating the invalidation.

5. The processor as in claim 1 wherein a mask value is to be used to uniquely identify each of the other TLBs to be notified.

6. The processor as in claim 1 further comprising:

fence instruction logic of each of the other cores to insert a fence operation in an instruction stream to cause any instructions in a pipeline of the other cores to wait until the fence operation is retired before accessing the TLBs of each of the other cores.

7. The processor as in claim 6 wherein the responses are to be sent from the TLBs of the other cores only after the fence operation has retired.

8. A method comprising:

caching a plurality of virtual-to-physical address translations in a translation lookaside buffer (TLB) usable by the set of one or more cores when executing the instructions;

locking a first page table entry (PTE) in the TLB to ensure that only one thread can modify the first PTE at a time, wherein the TLB is to modify the first PTE upon acquiring the lock;

executing a PTE invalidate instruction on a first core to invalidate the first PTE in other TLBs of other cores, the PTE invalidation circuit, responsive to execution of the PTE invalidate instruction, to responsively determine a number of other TLBs of other cores which need to be notified of the PTE invalidation, transmit PTE invalidate messages to the other TLBs, and wait for responses; and

releasing the lock on the first PTE responsive to receiving responses from all of the other TLBs, wherein an invalidation PTE state machine circuit to be programmed with a count value initially set to the number of other TLBs which need to be notified, the invalidation PTE state machine circuit to decrement the count value upon receiving each response from each of the other TLBs, and wherein the lock on the first PTE is released when the count value has been decremented to a threshold value.

9. The method as in claim 8 wherein the locking circuitry is to implement a mutex operation to acquire the lock on the first PTE.

10. The method as in claim 8 wherein each TLB comprises PTE invalidate request handling circuitry to receive invalidation requests transmitted from other TLBs, the invalidate request handling circuitry to responsively cause the TLBs to invalidate one or more PTEs identified in the invalidation requests and transmit a response indicating the invalidation.

11. The method as in claim 8 wherein a mask value is to be used to uniquely identify each of the other TLBs to be notified.

12. The method as in claim 8 further comprising:

fence instruction logic of each of the other cores to insert a fence operation in an instruction stream to cause any instructions in a pipeline of the other cores to wait until the fence operation is retired before accessing the TLBs of each of the other cores.

13. The method as in claim 12 wherein the responses are to be sent from the TLBs of the other cores only after the fence operation has retired.

14. A system comprising:

a memory to store instructions and data;

a processor to execute the instructions and process the data;

a graphics processor to perform graphics operations in response to graphics instructions;

a network interface to receive and transmit data over a network;

an interface for receiving user input from a mouse or cursor control device, the plurality of cores executing the instructions and processing the data responsive to the user input;

the processor comprising;

a plurality of cores to execute instructions and process data;

a translation lookaside buffer (TLB) comprising a plurality of entries to cache virtual-to-physical address translations usable by at least one of the plurality of cores when executing the instructions;

locking circuitry to allow a thread to lock a first page table entry (PTE) in the TLB to ensure that only one thread can modify the first PTE at a time, wherein the TLB is to modify the first PTE upon the thread acquiring the lock;

a PTE invalidation circuit to execute a PTE invalidate instruction on a first core to invalidate the first PTE in other TLBs of other cores, the PTE invalidation circuit, responsive to execution of the PTE invalidate instruction, to responsively determine a number of other TLBs of other cores which need to be notified of the PTE invalidation, transmit PTE invalidate messages to the other TLBs, and wait for responses;

the locking circuitry to release the lock on the first PTE responsive to receiving responses from all of the other TLBs; and

an invalidation PTE state machine circuit to be programmed with a count value initially set to the number of other TLBs which need to be notified, the invalidation PTE state machine circuit to decrement the count value upon receiving each response from each of the other TLBs, the locking circuitry to release the lock when the count value has been decremented to a threshold value.

15. The system as in claim 14 wherein the locking circuitry is to implement a mutex operation to acquire the lock on the first PTE.

16. The system as in claim 14 wherein each TLB comprises PTE invalidate request handling circuitry to receive invalidation requests transmitted from other TLBs, the invalidate request handling circuitry to responsively cause the TLBs to invalidate one or more PTEs identified in the invalidation requests and transmit a response indicating the invalidation.

17. The system as in claim 14 wherein a mask value is to be used to uniquely identify each of the other TLBs to be notified.

18. The system as in claim 14 further comprising:

fence instruction logic of each of the other cores to insert a fence operation in an instruction stream to cause any instructions in a pipeline of the other cores to wait until the fence operation is retired before accessing the TLBs of each of the other cores.

19. The system as in claim 18 wherein the responses are to be sent from the TLBs of the other cores only after the fence operation has retired.