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Apparatus and method for low-overhead synchronous page table updates

  • US 10,067,870 B2
  • Filed: 04/01/2016
  • Issued: 09/04/2018
  • Est. Priority Date: 04/01/2016
  • Status: Active Grant
First Claim
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1. A processor comprising:

  • a plurality of cores to execute instructions and process data;

    one or more translation lookaside buffers (TLBs) comprising a plurality of entries to cache virtual-to-physical address translations usable by at least one of the plurality of cores when executing the instructions;

    a page table entry (PTE) invalidation circuit to execute a PTE invalidate instruction on a first core to invalidate a first PTE in TLBs of other cores, the PTE invalidation circuit, responsive to execution of the PTE invalidate instruction, to responsively determine a number of other TLBs of other cores which need to be notified of the PTE invalidation, transmit PTE invalidate messages to the other TLBs, and wait for responses;

    locking circuitry to allow a thread to lock the first PTE in the first TLB to ensure that only one thread can modify the first PTE at a time; and

    an invalidation PTE state machine circuit to be programmed with a count value initially set to the number of other TLBs which need to be notified, the invalidation PTE state machine circuit to decrement the count value upon receiving each response from each of the other TLBs, the locking circuitry to release the lock when the count value has been decremented to a threshold value.

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