Apparatus and method to support a storage mode over a cache-line memory interface to a non-volatile memory dual in line memory module

• US 10,067,879 B2
• Filed: 12/16/2015
• Issued: 09/04/2018
• Est. Priority Date: 12/16/2015
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Han, Woojong, Rudoff, Andy M., Schmisseur, Mark A., Mangold, Richard P.
• Primary Examiner(s): Choe, Yong
• Application Number:
  US14/972,053
• Publication Number:
  US 20170177496A1
• Time in Patent Office: 993 Days
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0873 Mapping of cache memory to specific storage devices or parts thereof
• CPC Class Codes: G06F 12/0877 Cache access modes
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/152 Virtualized environment, e.g. logically partitioned system
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Abstract

Provided are an apparatus and method for using block windows configured in a memory module to provide block level access to memory chips in the memory module. A plurality of block windows are configured that map to addresses corresponding to the addressable locations in the memory chips. A read/write request is received indicating a requested read or write operation with respect to a target block window comprising one of the block windows. The requested read or write operation is performed with respect to the addresses that map to the target block window.

Claims

1. A memory module apparatus for receiving read and write operations from a host processor in a system, comprising:

at least one memory chip to store data in addressable locations;

a memory module controller to perform read and write operations with respect to the memory chips, the memory module controller to;

configure a plurality of block windows in storage areas of the memory module controller that map to addresses corresponding to the addressable locations in the memory chips;

receive a read or write operation with respect to a target block window comprising one of the block windows; and

perform the read or write operation with respect to the addresses that map to the target block window.

2. The memory module apparatus of claim 1, wherein the memory module apparatus comprises a non-volatile Dual In-Line Memory Module (NVDIMM) and wherein the memory module controller provides cache line memory access to the at least one memory chip and uses the block windows to provide storage block access to the at least one memory chip.

3. The memory module apparatus of claim 1, wherein the memory module controller is further to:

configure control registers for each block window of the block windows to indicate an address range of the addresses of the block window; and

in response to receiving the read or write operation, determine from the control registers, for the target block window, target addresses mapping to the target block window, wherein the read or write operation is performed with respect to the determined target addresses.

4. The memory module apparatus of claim 3, wherein the memory module controller is further to:

configure status registers for each block window to indicate a status of an operation with respect to the addresses that map to the block window; and

indicate a status of the read or write operation in the status registers for the target block window.

5. The memory module apparatus of claim 4, wherein the read or write operation comprises a read operation from a host block driver, wherein the memory module controller is further to:

return read data for the read operation read from the target addresses to the host block driver; and

return information on the status of the read operation from the status registers for the target block window to the host block driver.

6. The memory module apparatus of claim 3, wherein the memory module controller is further to:

indicate an operation type of a plurality of operation types in the control registers for each block window to indicate the operation type that is permitted with respect to the block window; and

in response to receiving the read or write operation, determine whether the read or write operation is permitted by the operation type indicated in the control registers for the target block window, wherein the read or write operation is performed in response to determining that the read or write operation is permitted by the operation type indicated in the control registers.

7. The memory module apparatus of claim 3, wherein the control registers for each block window of the block windows indicates a base address at which the address range mapping to the block window starts, and wherein the read or write operation indicates an address offset from the base address for the target block window at which the target addresses start, wherein to determine the target addresses comprises:

combine the address offset with the base address for the target block window to determine a starting address of the target addresses, wherein the target addresses extend from the starting address for the read or write operation.

8. The memory module apparatus of claim 1, wherein multiple read and write operations can be concurrently processed by the memory module controller against addresses mapping to multiple of the block windows and concurrently processed to different cache lines for mapping to addresses in one of the block windows.

9. The memory module apparatus of claim 1, wherein the memory module controller is further to:

receive, from a Basic Input Operating System (BIOS) in the system, commands to configure a block mode address range of the at least one memory chip to function as a storage device, wherein the block windows are configured within the block mode address range;

receive a request to configure block windows in a requested address range of the memory chips;

determine whether requested address range in which to configure the block windows is within the block mode address range;

fail the request to configure block windows in response to determining that the requested address range to configure is outside of the block mode address range; and

indicate an error in a status register of the request to configure block windows outside of the block mode address range.

10. The memory module apparatus of claim 1, wherein a host block driver executing in an operating system of the system sends commands to the memory module controller to configure the plurality of the block windows.

11. A system, comprising:

a host having a block driver; and

at least one memory module that receives read and write operations from the host, each memory module comprising;

memory chips for storing data in addressable locations;

a memory module controller that performs read and write operations with respect to the memory chips, to;

configure a plurality of block windows in storage areas of the memory module controller that map to addresses corresponding to the addressable locations in the memory chips;

receive from the block driver a read or write operation with respect to a target block window comprising one of the block windows; and

perform the read or write operation with respect to the addresses that map to the target block window.

12. The system of claim 11, wherein the memory module controller is further to:

configure control registers for each block window of the block windows to indicate an address range of the addresses of the block window; and

in response to receiving the requested read or write operation from the block driver, determine from the control registers, for the target block window, target addresses mapping to the target block window, wherein the read or write operation is performed with respect to the determined target addresses.

13. The system of claim 12, wherein the memory module controller is further to:

indicate an operation type of a plurality of operation types in the control registers for each block window to indicate the operation type that is permitted with respect to the block window; and

in response to receiving the requested read or write operation from the block driver, determine whether the read or write operation is permitted by the operation type indicated in the control registers for the target block window, wherein the read or write operations is performed in response to determining that the read or write operation is permitted by the operation type indicated in the control registers.

14. The system of claim 11, wherein multiple read and write operations from the block driver can be concurrently processed by the memory module controller against addresses mapping to multiple of the block windows and concurrently processed to different cache lines for mapping to addresses in one of the block windows.

15. The system of claim 11, further comprising:

a Basic Input Operating System (BIOS),

wherein the memory module controller is further to;

receive, from the BIOS, commands to configure a block mode address range of the memory chips to function as a storage device, wherein the block windows are configured within the block mode address range;

receive from the block driver a request to configure block windows in a requested address range of the memory chips;

determine whether requested address range in which to configure the block windows is within the block mode address range;

fail the request to configure block windows in response to determining that the requested address range to configure is outside of the block mode address range; and

indicate an error in a status register of the request to configure block windows outside of the block mode address range.

16. The system of claim 11, wherein the block driver sends commands to the memory module controller to configure the plurality of the block windows.

17. A method for processing read and write operations from a host processor with respect to memory chips in a memory module, comprising:

configuring a plurality of block windows in storage areas of a memory module controller that map to addresses corresponding to addressable locations in the memory chips;

receiving a read or write operation with respect to a target block window comprising one of the block windows; and

performing the read or write operation with respect to the addresses that map to the target block window.

18. The method of claim 17, further comprising:

configuring control registers for each block window of the block windows to indicate an address range of the addresses of the block window; and

in response to receiving the read or write operation, determining from the control registers, for the target block window, target addresses mapping to the target block window, wherein the read or write operation is performed with respect to the determined target addresses.

19. The method of claim 18, further comprising:

configuring status registers for each block window to indicate a status of an operation with respect to the addresses that map to the block window; and

indicating a status of the read or write operation in the status registers for the target block window.

20. The method of claim 18, further comprising:

indicating an operation type of a plurality of operation types in the control registers for each block window to indicate the operation type that is permitted with respect to the block window; and

in response to receiving the read or write operation, determining whether the read or write operation is permitted by the operation type indicated in the control registers for the target block window, wherein the read or write operation is performed in response to determining that the read or write operation is permitted by the operation type indicated in the control registers.

21. The method of claim 17, wherein multiple read and write operations can be concurrently processed by the memory module controller against addresses mapping to multiple of the block windows and concurrently processed to different cache lines for mapping to addresses in one of the block windows.

22. The method of claim 17, further comprising:

receiving from a Basic Input Operating System (BIOS) commands to configure a block mode address range of the memory chips to function as a storage device, wherein the block windows are configured within the block mode address range;

receiving a request to configure block windows in a requested address range of the memory chips;

determining whether requested address range in which to configure the block windows is within the block mode address range;

failing the request to configure block windows in response to determining that the requested address range to configure is outside of the block mode address range; and

indicating an error in a status register of the request to configure block windows outside of the block mode address range.

23. A memory module controller for use with a memory module having a plurality of memory chips that receives read and write operations from a host processor in a system, wherein the memory module controller has logic to:

configure a plurality of block windows in storage areas of the memory module controller that map to addresses corresponding to addressable locations in the memory chips;

receive a read or write operation with respect to a target block window comprising one of the block windows; and

perform the read or write operation with respect to the addresses that map to the target block window.

24. The memory module controller of claim 23, further to:

configure control registers for each block window of the block windows to indicate an address range of the addresses of the block window; and

in response to receiving the read or write operation, determine from the control registers, for the target block window, target addresses mapping to the target block window, wherein the read or write operation is performed with respect to the determined target addresses.

25. The memory module controller of claim 24, further to:

indicate an operation type of a plurality of operation types in the control registers for each block window to indicate the operation type that is permitted with respect to the block window; and

in response to receiving the read or write operation, determine whether the read or write operation is permitted by the operation type indicated in the control registers for the target block window, wherein the read or write operation is performed in response to determining that the read or write operation is permitted by the operation type indicated in the control registers.