Microwave integrated quantum circuits with cap wafer and methods for making the same

• US 10,068,181 B1
• Filed: 04/27/2016
• Issued: 09/04/2018
• Est. Priority Date: 04/27/2015
• Status: Active Grant

• Current Assignee: Rigetti & Co., Inc.
• Original Assignee: Rigetti & Co., Inc.
• Inventors: Rigetti, Chad T., Vahidpour, Mehmoosh, Thompson, Dane Christoffer, Marchenokov, Alexei N., Sete, Eyob Alebachew, Orgiazzi, Jean-Luc Francois-Xavier
• Primary Examiner(s): Nguyen, Sophia
• Application Number:
  US15/140,273
• Time in Patent Office: 860 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G06N 10/00 Quantum computing, i.e. information processing based on quantum-mechanical phenomena
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76891 by using superconducting materials
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/16235 Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H10N 60/12 Josephson-effect devices
• CPC Class Codes: H10N 60/815 for Josephson-effect devices
• CPC Class Codes: H10N 69/00 Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
• CPC Class Codes: Y10S 977/933 Spintronics or quantum computing

Abstract

A quantum computing system that includes a quantum circuit device having at least one operating frequency; a first substrate having a first surface on which the quantum circuit device is disposed; a second substrate having a first surface that defines a recess of the second substrate, the first and second substrates being arranged such that the recess of the second substrate forms an enclosure that houses the quantum circuit device; and an electrically conducting layer that covers at least a portion of the recess of the second substrate.

Claims

1. A quantum computing system comprising:

a quantum circuit device;

a first substrate having a first surface on which the quantum processing device is disposed and a second, opposing surface;

a second substrate having a first surface; and

bonding elements in contact with one of the surfaces of the first substrate and the first surface of the second substrate,

wherein the first surface of the second substrate forms a recess,

wherein the first and second substrates are arranged such that the recess forms an enclosure that hosts the quantum circuit device,

wherein the recess includes channels that allow for gas trapped inside the recess to be pumped out.

2. The quantum computing system of claim 1, wherein the quantum circuit device is one of a qubit, a tunable quantum coupler, a readout circuit including one or more linear resonators or one or more non-linear resonators, a filter, a quantum amplifier, or a circulator.

3. The quantum computing system of claim 1, further comprising:

an electrically conducting layer disposed on the first surface of the second substrate that covers at least a portion of the recess,

wherein the bonding elements form an electromagnetic contact between the electrically conducting layer and structures of the first substrate that are grounded during operation of the quantum computing system.

4. The quantum computing system of claim 3, wherein the recess of the second substrate creates a capacitance between a circuit and the bottom of the recess.

5. The quantum computing system of claim 3, wherein the recess of the second substrate reduces a participation ratio of the first substrate by increasing a capacitance between a circuit and the bottom of the recess.

6. The quantum computing system of claim 3, wherein the recess of the second substrate isolates circuit components from interacting with spurious modes and surface loss to improve coherence times of the circuit components.

7. The quantum computing system of claim 3, wherein the recess of the second substrate provides controlled coupling between neighboring circuit components.

8. The quantum computing system of claim 3, wherein the recess of the second substrate reduces cross couplings between circuit components.

9. The quantum computing system of claim 1, wherein the second substrate comprises one of silicon, sapphire, silicon oxide, silicon nitride, quartz, lithographically defined thick photoresists (SU8) or an electrical conducting material that is a superconducting material when the quantum computing system is operated.

10. The quantum computing system of claim 9, wherein the second substrate comprises lithographically defined thick photoresist.

11. The quantum computing system of claim 1, wherein the bonding elements comprise bumps that include an electrically conducting material that is a superconducting material when the quantum computing system is operated.

12. The quantum computing system of claim 11, wherein the electrically conducting material is selected from the group consisting of Indium, aluminum, and palladium.

13. The quantum computing system of claim 11, wherein the bumps are arranged to form channels that allow for gas trapped between the bumps to be pumped out.

14. The quantum computing system of claim 11, further comprising:

bond pads disposed on one of the surfaces of the first substrate or the first surface of the second substrate, opposing the other surface on which the bumps are disposed.

15. The quantum computing system of claim 14, wherein the bond pads comprise one of aluminum, indium or Ti.

16. The quantum computing system of claim 14, wherein the bond pads comprise a cap layer of one of aluminum, indium or Ti.

17. The quantum computing system of claim 11, further comprising:

an Al layer deposited on one of the surfaces of the first substrate or the first surface of the second substrate; and

Under Bump Metallization (UBM) formed on the Al layer, the UBM being a wettable and solderable material to facilitate bonding to aluminum which has a surface oxide and not solderable.

18. The quantum computing system of claim 17, wherein the UBM comprises platinum.

19. The quantum computing system of claim 17, wherein the UBM comprises palladium.

20. The quantum computing system of claim 1, further comprising:

spacers disposed on one of the surfaces of the first substrate or the second substrate that face each other,

wherein the spacers are in contact with the surfaces of the first substrate and the second substrate that face each other to cause a separation thereof that is substantially equal to a height of the spacers.

21. The quantum computing system of claim 20, wherein the spacers comprise insulating standoff bumps.

22. The quantum computing system of claim 21, wherein the standoff bumps include one of Si Oxide or Si Nitride.

23. The quantum computing system of claim 21, wherein the standoff bumps form a non-hermetic connection between the first and second substrates that allows for gas trapped inside the recess of the second substrate to be pumped out.

24. The quantum computing system of claim 21, further comprising:

an electrically conducting layer disposed on the first surface of the second substrate that conforms to the insulating standoff bumps.

25. The quantum computing system of claim 24, wherein the electrically conducting layer comprises one of aluminum, indium or Ti.

26. The quantum computing system of claim 24, wherein the electrically conducting layer comprises aluminum.

27. The quantum computing system of claim 24, wherein the electrically conducting layer comprises indium.

28. The quantum computing system of claim 24, wherein the electrically conducting layer comprises titanium.

29. The quantum computing system of claim 1 wherein the quantum computing system comprises at least one device from the group of devices comprised of an integrated quantum processing device, a quantum memory device, a filter device, a circulator device, and a quantum amplifier device.

30. The quantum computing system of claim 1, wherein the recess also forms an enclosure that hosts a coupling line connecting two or more quantum circuit devices.

31. The quantum computing system of claim 1, wherein the bonding elements are covered with nanoparticles.

32. The quantum computing system of claim 31, wherein the nanoparticles comprise diamond.

33. The quantum computing system of claim 31, wherein the nanoparticles have sharp edges.

34. A method of fabricating a quantum computing system, the method comprising:

forming a quantum circuit device on a first substrate, the first substrate having a first surface on which the quantum processing device is disposed and a second, opposing surface;

forming bonding elements adapted to contact one of the surfaces of the first substrate and a first surface of a second substrate;

forming spacers on one of the surfaces of the first substrate or the second substrate adapted to face each other, wherein the spacers are adapted to contact the surfaces of the first substrate and the second substrate adapted to face each other to cause a separation thereof that is substantially equal to a height of the spacers, and the spacers comprise insulating standoff bumps; and

forming an electrically conducting layer disposed on the first surface of the second substrate that conforms to the insulating standoff bumps.

35. The method of claim 34, further comprising:

etching one or more recesses in the first surface of the second substrate; and

bonding the first substrate and the second substrate such that the one or more recesses form respective enclosures that house the quantum circuit device.

36. The method of claim 35, wherein the etching of the recesses of the second substrate is performed using either Deep Reactive Ion Etch process or a wet etch process with lithographic mask or machining.

37. The method of claim 35, wherein the etching of the recesses of the second substrate is performed to at least one specified depth using at least one lithographic mask and at least one etch stop layer.

38. The method of claim 37, wherein the etch stop layer comprises one of Si Oxide, Si Nitride, or Al oxide.

39. The method of claim 35, wherein the bonding of the first substrate and the second substrate is performed by applying pressure on one or both of the substrates to be bonded.

40. The method of claim 39, wherein the standoff bumps form a gap between the substrates to be bonded to control a bonding force.

41. The method of claim 39, wherein a die bonder or a wafer bonder is used to align and bond the substrates to be bonded.

42. The method of claim 39, further comprising:

dispersing nanoparticles over the bonding elements to break the oxide layers from both first and second substrates.

43. The method of claim 42, wherein the nanoparticles comprise diamond.

44. The method of claim 42, wherein the nanoparticles have sharp edges to break oxide layers of the bonding elements.

45. The method of claim 42, wherein the dispersing of the nanoparticles is performed by submersing the bonding elements in a solution containing the nanoparticles.

46. The method of claim 35, wherein the bonding results in a low DC-resistance contact between the bonded substrates.

47. The method of claim 34, wherein one or more of the forming operations are performed using a lithographic mask is one of photoresist, silicon oxide, or silicon nitride.

48. The method of claim 34, wherein the forming of the electrically conducting layer is performed by sputtering, e beam evaporation, atomic layer deposition (ALD), Metal Organic Chemical Vapor Deposition (MOCVD) or electroplating.

49. The method of claim 34, wherein the standoff bumps are thermally grown or deposited using one of LPCVD or PECVD.

50. The method of claim 34, further comprising:

depositing an adhesion layer on the electrically conducting layer,

wherein the bonding elements are formed on the adhesion layer.

51. The method of claim 50, wherein the adhesion layer comprises an electrically conducting material that is a superconducting material when the quantum computing system is operated.

52. The method of claim 51, wherein the electrically conducting material of the adhesion layer comprises one of Ti, Ta.

53. The method of claim 50, wherein the adhesion layer is deposited by one of sputtering, evaporation, or electroplating.

54. The method of claim 34, wherein the bonding elements are formed via one of sputtering, evaporation, or electroplating.

55. The method of claim 34, wherein the bonding elements are formed to be longer than the standoff bumps.

56. The method of claim 55, wherein the bonding elements are formed using one of lift-off resist, spray on resist, wet or dry etching.

57. A quantum computing system comprising:

a quantum circuit device;

a first substrate having a first surface on which the quantum processing device is disposed and a second, opposing surface;

a second substrate having a first surface;

bonding elements in contact with one of the surfaces of the first substrate and the first surface of the second substrate;

spacers disposed on one of the surfaces of the first substrate or the second substrate that face each other, wherein the spacers are in contact with the surfaces of the first substrate and the second substrate that face each other to cause a separation thereof that is substantially equal to a height of the spacers, and the spacers comprise insulating standoff bumps; and

an electrically conducting layer disposed on the first surface of the second substrate that conforms to the insulating standoff bumps.

58. The quantum computing system of claim 57, wherein the quantum circuit device is one of a qubit, a tunable quantum coupler, a readout circuit including one or more linear resonators or one or more non-linear resonators, a filter, a quantum amplifier, or a circulator.

59. The quantum computing system of claim 57, wherein

the first surface of the second substrate forms a recess, and

the first and second substrates are arranged such that the recess forms an enclosure that hosts the quantum circuit device.

60. The quantum computing system of claim 59, wherein the electrically conducting layer disposed on the first surface of the second substrate covers at least a portion of the recess,

wherein the bonding elements form an electromagnetic contact between the electrically conducting layer and structures of the first substrate that are grounded during operation of the quantum computing system.

61. The quantum computing system of claim 60, wherein the recess of the second substrate creates a capacitance between a circuit and the bottom of the recess.

62. The quantum computing system of claim 60, wherein the recess of the second substrate reduces a participation ratio of the first substrate by increasing a capacitance between a circuit and the bottom of the recess.

63. The quantum computing system of claim 60, wherein the recess of the second substrate isolates circuit components from interacting with spurious modes and surface loss to improve coherence times of the circuit components.

64. The quantum computing system of claim 60, wherein the recess of the second substrate provides controlled coupling between neighboring circuit components.

65. The quantum computing system of claim 60, wherein the recess of the second substrate reduces cross couplings between circuit components.

66. The quantum computing system of claim 59, wherein the second substrate comprises one of silicon, sapphire, silicon oxide, silicon nitride, quartz, lithographically defined thick photoresists (SU8) or an electrical conducting material that is a superconducting material when the quantum computing system is operated.

67. The quantum computing system of claim 57, further comprising:

a second quantum circuit device disposed on the first surface of the second substrate,

wherein the bonding elements are in contact with the second surface of the first substrate.

68. The quantum computing system of claim 67, wherein the bonding elements form an electromagnetic contact between the first and second substrates through which the quantum circuit devices respectively disposed on the first and second substrates are coupled to each other.

69. The quantum computing system of claim 67, wherein the bonding elements form an electromagnetic contact between the bonded first and second substrates through which the quantum circuit device disposed on the first substrate receives DC signals or MW signals from signal lines of the second substrate.

70. The quantum computing system of claim 57, wherein the bonding elements comprise bumps that include an electrically conducting material that is a superconducting material when the quantum computing system is operated.

71. The quantum computing system of claim 70, wherein the electrically conducting material is selected from the group consisting of Indium, aluminum, and palladium.

72. The quantum computing system of claim 70, wherein the bumps are arranged to form channels that allow for gas trapped between the bumps to be pumped out.

73. The quantum computing system of claim 70, further comprising:

bond pads disposed on one of the surfaces of the first substrate or the first surface of the second substrate, opposing the other surface on which the bumps are disposed.

74. The quantum computing system of claim 73, wherein the bond pads comprise one of aluminum, indium or Ti.

75. The quantum computing system of claim 73, wherein the bond pads comprise a cap layer of one of aluminum, indium or Ti.

76. The quantum computing system of claim 70, further comprising:

an Al layer deposited on one of the surfaces of the first substrate or the first surface of the second substrate; and

Under Bump Metallization (UBM) formed on the Al layer, the UBM being a wettable and solderable material to facilitate bonding to aluminum which has a surface oxide and not solderable.

77. The quantum computing system of claim 57, wherein the standoff bumps include one of Si Oxide or Si Nitride.

78. The quantum computing system of claim 57, wherein the standoff bumps form a non-hermetic coection between the first and second substrates that allows for gas trapped inside a recess of the second substrate to be pumped out.

79. The quantum computing system of claim 57, wherein the electrically conducting layer comprises aluminum.

80. The quantum computing system of claim 57, wherein the electrically conducting layer comprises indium.

81. The quantum computing system of claim 57, wherein the electrically conducting layer comprises titanium.

82. The quantum computing system of claim 57, wherein the quantum computing system comprises at least one device from the group of devices comprised of an integrated quantum processing device, a quantum memory device, a filter device, a circulator device, and a quantum amplifier device.