Apparatus for low power write and read operations for resistive memory
First Claim
1. An apparatus comprising:
- a resistive memory cell coupled to a bit line and a select line;
a first pass-gate coupled to the bit line;
a second pass-gate coupled to the select line; and
a multiplexer operable by an input data, wherein the input data is data to be stored in the resistive memory cell, and wherein the multiplexer is to provide a control signal to the first and second pass-gates according to a logic level of the input data.
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Accused Products
Abstract
Apparatuses for improving resistive memory energy efficiency are provided. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.
18 Citations
9 Claims
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1. An apparatus comprising:
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a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by an input data, wherein the input data is data to be stored in the resistive memory cell, and wherein the multiplexer is to provide a control signal to the first and second pass-gates according to a logic level of the input data. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A system comprising:
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a processor; a wireless interface to allow the processor to communicate with another device; a memory coupled to the processor, the memory having apparatus which includes; a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by an input data, wherein the input data is data to be stored in the resistive memory cell, and wherein the multiplexer is to provide a control signal to the first and second pass-gates according to a logic level of the input data; and a display unit to display content processed by the processor. - View Dependent Claims (9)
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Specification