Integrated circuit comprising at least an integrated antenna

• US 10,068,961 B2
• Filed: 02/14/2017
• Issued: 09/04/2018
• Est. Priority Date: 07/28/2011
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pagani, Alberto, Finocchiaro, Alessandro
• Primary Examiner(s): Roman, Angel
• Application Number:
  US15/431,877
• Publication Number:
  US 20170154948A1
• Time in Patent Office: 567 Days
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 29/0642 : Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

An integrated circuit on a substrate includes a peripheral portion that surrounds an active area and is positioned close to a scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in the peripheral portion on different planes of metallizations starting from the substrate and forms an integrated antenna. Another conductive structure extends in the peripheral portion on different planes of metallizations and forms a seal ring.

Claims

1. An integrated circuit, comprising:

a substrate having a top surface;

an insulating region above the top surface, said insulating region including a peripheral portion adjacent to a scribe line, said peripheral portion including metallizations;

an antenna structure formed by antenna lines arranged in a plurality of planes of said metallizations; and

a seal ring formed by metal layers arranged in a plurality of planes of said metallizations and interconnected by vias;

wherein the insulating region insulates the antenna lines of the antenna structure from the metal layers and vias of the seal ring; and

an opening in an upper surface of the insulating region to expose a top surface of a top-most one of the metal layers of the seal ring to provide a contact pad for making an external electrical connection.

2. The integrated circuit of claim 1, wherein at least one of the metal layers of the seal ring extends underneath at least one antenna line of the antenna structure and further extends into the scribe line.

3. The integrated circuit of claim 2, further comprising a metallization line extending within the scribe line, wherein said metallization line is electrically connected by a via to said at least one of the metal layers of the seal ring that extends into the scribe line.

4. The integrated circuit of claim 3, further comprising Test Element Group (TEG) circuits in the scribe line electrically connected to the metallization line extending within the scribe line.

5. The integrated circuit of claim 3, wherein the substrate is doped with a first conductivity type and further comprising a well region within the substrate doped with a second conductivity type opposite the first conductivity type, and wherein the seal ring is electrically connected to the well region within the substrate doped with the second conductivity type.

6. The integrated circuit of claim 1, wherein at least one of the metal layers of the seal ring extends underneath at least one antenna line of the antenna structure and further extends into an active area of the integrated circuit.

7. The integrated circuit of claim 6, wherein said antenna structure and seal ring surround the active area of the integrated circuit.

8. The integrated circuit of claim 7, wherein a portion of the antenna structure is located between the seal ring and the active area of the integrated circuit.

9. The integrated circuit of claim 8, wherein a further portion of the antenna structure is located between the seal ring and the scribe line.

10. The integrated circuit of claim 1, wherein the antenna lines of the antenna structure form at least two antennas coupled to form a transformer.

11. The integrated circuit of claim 1, wherein the seal ring includes a first group of metal layers arranged in the plurality of planes of said metallizations and interconnected by first vias and a second group of metal layers arranged in the plurality of planes of said metallizations and interconnected by second vias, and wherein said top-most one of the metal layers of the seal ring providing the contact pad is connected by vias to both the first group and second group, and wherein metal layers of the first and second groups on a same plane are insulated from each other by the insulating region.

12. The integrated circuit of claim 11, wherein a portion of the antenna structure passes between the first group and second group and underneath said top-most one of the metal layers of the seal ring providing the contact pad.

13. The integrated circuit of claim 11, wherein the substrate is doped with a first conductivity type and further comprising a first well region within the substrate doped with a second conductivity type opposite the first conductivity type and a second well region within the substrate doped with the second conductivity type opposite the first conductivity type, and wherein the first group is electrically connected to the first well region within the substrate doped with the second conductivity type and wherein the second group is electrically connected to the second well region within the substrate doped with the second conductivity type.

14. The integrated circuit of claim 11, wherein at least one of the metal layers of the first group extends into the scribe line.

15. The integrated circuit of claim 14, further comprising a metallization line extending within the scribe line, wherein said metallization line is electrically connected by a via to said at least one of the metal layers of the first group that extends into the scribe line.

16. The integrated circuit of claim 15, further comprising Test Element Group (TEG) circuits in the scribe line electrically connected to the metallization line extending within the scribe line.

17. The integrated circuit of claim 11, wherein at least one of the metal layers of the second group extends into an active area of the integrated circuit.

18. The integrated circuit of claim 17, wherein said antenna structure and seal ring surround the active area of the integrated circuit.

19. The integrated circuit of claim 18, wherein the second group is located between the antenna structure and the active area of the integrated circuit.

20. The integrated circuit of claim 19, wherein the first group is located between the antenna structure and the scribe line.

21. An integrated circuit, comprising:

a substrate having a top surface;

an insulating region above the top surface, said insulating region including a peripheral portion adjacent to a scribe line, said peripheral portion including metallizations;

an antenna structure formed by antenna lines arranged in a plurality of planes of said metallizations; and

a seal ring formed by metal layers arranged in a plurality of planes of said metallizations and interconnected by vias;

wherein the insulating region insulates the antenna lines of the antenna structure from the metal layers and vias of the seal ring; and

wherein at least one of the metal layers of the seal ring extends underneath at least one antenna line of the antenna structure and further extends into the scribe line.

22. The integrated circuit of claim 21, further comprising a metallization line extending within the scribe line, wherein said metallization line is electrically connected by a via to said at least one of the metal layers of the seal ring that extends into the scribe line.

23. The integrated circuit of claim 22, further comprising Test Element Group (TEG) circuits in the scribe line electrically connected to the metallization line extending within the scribe line.

24. The integrated circuit of claim 23, further comprising an opening in an upper surface of the insulating region to expose a top surface of a top-most one of the metal layers of the seal ring to provide a contact pad for making an external electrical connection to the TEG circuits.

25. The integrated circuit of claim 21, wherein said antenna structure and seal ring surround an active area of the integrated circuit.

26. The integrated circuit of claim 25, wherein a portion of the antenna structure is located between the seal ring and the active area of the integrated circuit.

27. The integrated circuit of claim 26, wherein a further portion of the antenna structure is located between the seal ring and the scribe line.

28. The integrated circuit of claim 24, wherein the seal ring includes a first group of metal layers arranged in the plurality of planes of said metallizations and interconnected by first vias and a second group of metal layers arranged in the plurality of planes of said metallizations and interconnected by second vias, and wherein said top-most one of the metal layers of the seal ring providing the contact pad is connected by vias to both the first group and second group, and wherein metal layers of the first and second groups on a same plane are insulated from each other by the insulating region.

29. The integrated circuit of claim 28, wherein a portion of the antenna structure passes between the first group and second group and underneath said top-most one of the metal layers of the seal ring providing the contact pad.