Termination design for high voltage device

• US 10,069,005 B2
• Filed: 02/06/2017
• Issued: 09/04/2018
• Est. Priority Date: 08/25/2011
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Guan, Lingpeng, Bhalla, Anup, Yilmaz, Hamza
• Primary Examiner(s): Doan, Theresa T
• Application Number:
  US15/425,235
• Publication Number:
  US 20170148910A1
• Time in Patent Office: 575 Days
• Field of Search: 257333, 257330-331, 438271
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

an epitaxial layer of the first conductivity type disposed on a top surface of the semiconductor substrate, wherein the epitaxial layer includes a surface shielded region that is heavily doped positioned above a voltage blocking region that is lightly doped;

an active cell array including a plurality of active semiconductor devices formed in the epitaxial layer; and

a termination region surrounding the active cell array, wherein the termination region includes a plurality of termination structures formed in the epitaxial layer, each of the termination structures comprising a trench lined with a dielectric material and filled with a conductive material as a trench shield electrode, and a buried doped-region of the second conductivity type surrounding at least a bottom portion of the trench, and wherein the termination region includes a body region of second conductivity type opposite to the first conductivity type at a top surface of the surface shielded region proximate to the trench shield electrodes,

wherein the plurality of termination structures has a first set of one or more termination structures, each termination structure in the first set including an electrical connection between the corresponding trench shield electrode and a portion of the adjacent body layer further away from the active cell array.

2. The device of claim 1 wherein the plurality of termination structures has a second set of one or more termination structures provided between the active cell array and the first set, each termination structure in the second set including an electrical connection between its corresponding trench shield electrode and a second portion of the adjacent body layer closer to the active cell array.

3. The device of claim 1, wherein the buried doped-regions are connected to the body layer by a link region of the second conductivity type, wherein the link region is disposed along sidewalls of the trenches.

4. The device of claim 3, wherein the plurality of termination structures has a third set of one or more termination structures adjacent to an edge of a device die, wherein a floating electrode formed between two adjacent termination structures in the third set, the floating electrode being configured to create a disconnect between the body layer and the link region.

5. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

an epitaxial layer of the first conductivity type disposed on a top surface of the semiconductor substrate, wherein the epitaxial layer includes a surface shielded region that is heavily doped positioned above a voltage blocking region that is lightly doped;

an active cell array including a plurality of active semiconductor devices formed in the epitaxial layer; and

a termination region surrounding the active cell array, wherein the termination region includes a plurality of termination structures formed in the epitaxial layer, each of the termination structures comprising a trench lined with a dielectric material and filled with a conductive material as a trench shield electrode, and a buried doped-region of the second conductivity type surrounding at least a bottom portion of the trench, and wherein the termination region includes a body region of second conductivity type opposite to the first conductivity type at a top surface of the surface shielded region proximate to the trench shield electrodes,

wherein the buried doped-regions are connected to the body layer by a link region of the second conductivity type, wherein the link region is disposed along sidewalls of the trenches,

wherein the plurality of termination structures has a first set of one or more termination structures adjacent to an edge of a device die, wherein a floating electrode formed between two adjacent termination structures in the first set, the floating electrode being configured to create a disconnect between the body layer and the link region.

6. The device of claim 5, wherein the plurality of termination structures has a second set of one or more termination structures closest to the active cell array, each termination structure in the second set including an electrical connection between its corresponding trench shield electrode and a first portion of the adjacent body layer closer to the active cell array.

7. The device of claim 6, wherein the plurality of termination structures has a third set of one or more termination structures adjacent to the first set, each termination structure in the third set including an electrical connection between its corresponding trench shield electrode and a second portion of the adjacent body layer further away from the active cell array.

8. The device of claim 6, wherein the plurality of termination structures has a third set of one or more termination structures provided between the first and second sets, each termination structure in the third set including an electrical connection between its corresponding trench shield electrode and a second portion of the adjacent body layer further away from the active cell array.