LED bypass and control circuit for fault tolerant LED systems

• US 10,070,491 B2
• Filed: 12/02/2015
• Issued: 09/04/2018
• Est. Priority Date: 05/22/2012
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: DeNicholas, Joseph V., Tsao, Perry, Goeltner, Christoph, Herrington, Daniel Ross, Masson, James, Patterson, James, Berns, Werner
• Primary Examiner(s): Le, Don
• Application Number:
  US14/957,052
• Publication Number:
  US 20160088699A1
• Time in Patent Office: 1,007 Days
• CPC Class Codes: H05B 45/10 Controlling the intensity of the light
• CPC Class Codes: H05B 45/375 using buck topology
• CPC Class Codes: H05B 45/48 having LEDs organised in strings and incorporating parallel shunting devices
• CPC Class Codes: H05B 45/54 in a series array of LEDs

Abstract

A light system (FIG. 2) is disclosed. The light system includes a plurality of series connected light emitting diodes (240-246). Each of a plurality of switching devices (230-236) has a control terminal and each has a current path coupled in parallel with a respective LED. A plurality of fault detector circuits (220-226) are each coupled in parallel with a respective light emitting diode. Each fault detector circuit has a first comparator (FIG. 7, 704) arranged to compare a voltage across the respective light emitting diode to a respective first reference voltage (708). When a fault is detected, a control signal is applied to the control terminal to turn on a respective switching device of the plurality of switching devices.

Claims

1. A register circuit, comprising:

a first set of addressable registers comprising a first subset, the first subset of registers comprising On registers of a light emitting diode (LED) light system and a second subset of registers, the second subset of registers comprising Off registers of the light emitting diode (LED) light system;

a logic circuit arranged to select only the first subset in response to a first sequence of K address signals, where K is a positive integer; and

the logic circuit arranged to select a first part of the first subset and a first part of the second subset in response to a second sequence of K address signals.

2. A light system as in claim 1, wherein a value in each On register determines when a respective LED turns on, and wherein a value in at least one Off register determines when the respective LED turns off.

3. A register circuit as in claim 1, comprising:

a second set of registers comprising a same number of registers as the first set of addressable registers; and

a switching circuit coupled between the first set of addressable registers and the second set of registers and arranged to transfer the contents of the first set of addressable registers to the second set of registers in response to a load signal.

4. A register circuit as in claim 3, wherein the first set of addressable registers comprises input registers, and wherein the second set of registers comprises pulse width modulation (PWM) registers.

5. A register circuit as in claim 1, comprising:

a second set of registers comprising a same number of registers as the first set of addressable registers; and

a switching circuit coupled between the first set of addressable registers and the second set of registers and arranged to transfer the contents of each register of the first set of addressable registers to a corresponding register of the second set of registers in response to a respective load signal.

6. A method of operating a light emitting diode (LED) light system, comprising:

writing data in a first set of registers, each register of the first set arranged to operate a respective LED of a first plurality of series connected LEDs;

writing data in a second set of registers, each register of the second set arranged to operate the respective LED of the first plurality of series connected LEDs;

incrementing a count in a first counter in response to a clock signal;

turning on each respective LED when a register of the first set matches a respective count of the first counter; and

turning off each respective LED when a register of the second set matches a respective count of the first counter.

7. A method as in claim 6, comprising:

writing data in the first set of registers so that each respective LED turns on in response to a different count of the first counter; and

writing data in the second set of registers so that each respective LED turns off in response to a different count of the first counter.

8. A method as in claim 6, comprising writing data in each register of the first and second sets of registers in a single clock cycle of the clock signal.

9. A method as in claim 6, comprising writing data in each register of only the first set of registers in a single clock cycle of the clock signal.

10. A method as in claim 6, comprising writing data in each register of only the second set of registers in a single clock cycle of the clock signal.

11. A method as in claim 6, comprising controlling a duty cycle of each LED of the first plurality of series connected LEDs by a difference between the data stored in each respective register of the first set of registers and the data stored in each respective register of the second set of registers.

12. A method as in claim 6, comprising:

writing data in a third set of registers, each register of the third set arranged to operate a respective LED of a second plurality of series connected LEDs;

writing data in a fourth set of registers, each register of the fourth set arranged to operate the respective LED of the second plurality of series connected LEDs;

incrementing a count in a second counter in response to the clock signal;

turning on each respective LED when a register of the third set matches a respective count of the second counter; and

turning off each respective LED when a register of the fourth set matches a respective count of the second counter.

13. A method as in claim 12, comprising synchronizing the first and second counters in response to a synchronization signal.