Self diagnostic accelerometer field programmable gate array (SDA FPGA)

• US 10,073,115 B1
• Filed: 04/18/2016
• Issued: 09/11/2018
• Est. Priority Date: 04/18/2016
• Status: Active Grant

• Current Assignee: U.S. Government Administrator of NASA (Government of the United States of America)
• Original Assignee: United States Administrator of National Aeronautics and Space Administration
• Inventors: Tokars, Roger P., Lekki, John D.
• Primary Examiner(s): Rogers, David A
• Application Number:
  US15/131,089
• Time in Patent Office: 876 Days
• CPC Class Codes: G01P 15/09 by piezoelectric pick-up
• CPC Class Codes: G01P 21/00 Testing or calibrating of apparatus or devices covered by the preceding groups

Abstract

A self-diagnostic accelerometer (SDA) field programmable gate array (FPGA) may be capable of real time or near-real time diagnostic processing to determine potential accelerometer issues during flight or other mission critical operational situations. The SDA FPGA may determine accelerometer structural health and an attachment condition using an electronics system that is smaller, more energy efficient, and more cost effective than previous diagnostic tools. Advantages of the system may include diagnosing sensors automatically, immediately, actively (i.e., confirming the fault), and consistently, without the influence of a human operator. Customizable SDA algorithms may be adjusted to the specific needs of the sensor/environment.

Claims

1. A system, comprising:

an accelerometer attached to a structure;

a field programmable gate array (FPGA) communicably coupled to the accelerometer; and

signal conditioning circuitry operably coupled to the FPGA and the accelerometer, wherein the FPGA is configured to provide a diagnostic signal to the signal conditioning circuitry, wherein;

the signal conditioning circuitry comprises;

a first band pass filter configured to receive, and reduce noise in, the diagnostic signal, and output a filtered diagnostic signal;

a first amplifier configured to receive the filtered diagnostic signal, amplify the filtered diagnostic signal, and output an amplified diagnostic signal to the accelerometer;

a capacitor configured to receive an accelerometer response signal and output a coupled response signal;

a second band pass filter configured to receive, and reduce noise in, the coupled response signal and output a filtered response signal; and

a second amplifier configured to receive the filtered response signal, amplify the filtered response signal, and output a modified accelerometer response signal,

the signal conditioning circuitry is configured to;

provide the diagnostic signal to the accelerometer,

receive the accelerometer response signal responsive to the diagnostic signal from the accelerometer, and

output the modified accelerometer response signal, and the FPGA is configured to;

receive the modified accelerometer response signal from the signal conditioning circuitry,

process the modified accelerometer response signal using one or more cross correlation algorithms stored thereon, and

output an indication of accelerometer health, an attachment condition, or both.

2. The system of claim 1, wherein the FPGA and signal conditioning circuitry are configured to analyze the accelerometer health, the attachment condition, or both, in real time.

3. The system of claim 1, wherein the structure is an aircraft or a space vehicle.

4. The system of claim 1, further comprising:

a display configured to receive the indication of accelerometer health, the attachment condition, or both, and display the indication.

5. The system of claim 1, wherein the accelerometer is a piezoelectric charge accelerometer.

6. The system of claim 1, wherein the diagnostic signal is a sinusoidal wave signal that sweeps from approximately 30 kHz to approximately 80 kHz.

7. The system of claim 1, wherein the FPGA comprises:

a high frequency diagnostic source configured to generate the diagnostic signal that is sent to the signal conditioning circuitry; and

data acquisition circuitry configured to receive the modified accelerometer response signal from the signal conditioning circuitry.

8. A self-diagnostic accelerometer (SDA) field programmable gate array (FPGA) system, comprising:

a plurality of accelerometers;

a FPGA communicably coupled to the plurality of accelerometers; and

signal conditioning circuitry operably coupled to the FPGA and the plurality of accelerometers, wherein the FPGA is configured to provide one or more diagnostic signals to the signal conditioning circuitry, wherein;

the signal conditioning circuitry comprises;

a first band pass filter configured to receive, and reduce noise in, a received diagnostic signal, and output a filtered diagnostic signal;

a first amplifier configured to receive the filtered diagnostic signal, amplify the filtered diagnostic signal, and output an amplified diagnostic signal to a respective accelerometer;

a capacitor configured to receive an accelerometer response signal and output a coupled response signal;

a second band pass filter configured to receive, and reduce noise in, the coupled response signal and output a filtered response signal; and

a second amplifier configured to receive the filtered response signal, amplify the filtered response signal, and output a modified accelerometer response signal,

the SDA circuitry is configured to;

provide the one or more amplified diagnostic signals to the plurality of accelerometers,

receive accelerometer response signals responsive to the diagnostic signal from each of the plurality of accelerometers, and

output modified accelerometer response signals, and

the FPGA is configured to;

receive the modified accelerometer response signals from the signal conditioning circuitry,

process the modified accelerometer response signals using one or more cross correlation algorithms stored thereon, and

output indications of health, an attachment condition, or both, for each of the plurality of accelerometers.

9. The SDA FPGA system of claim 8, wherein the FPGA and signal conditioning circuitry are configured to analyze the health, the attachment conditions, or both, for the plurality of accelerometers in real time.

10. The SDA FPGA system of claim 8, wherein the system is operably connected to or otherwise configured art part of an aircraft or a space vehicle.

11. The SDA FPGA system of claim 8, wherein the plurality of accelerometers each receive a same diagnostic signal.

12. The system of claim 8, wherein the one or more diagnostic signals are sinusoidal wave signals that sweep from approximately 30 kHz to approximately 80 kHz.

13. A field programmable gate array (FPGA), comprising:

a high frequency diagnostic source configured to generate a diagnostic signal that is sent to self-diagnostic accelerometer (SDA) circuitry,

wherein the SDA circuitry comprises;

a first band pass filter configured to receive, and reduce noise in, the diagnostic signal, and output a filtered diagnostic signal;

a first amplifier configured to receive the filtered diagnostic signal, amplify the filtered diagnostic signal, and output an amplified diagnostic signal to a respective accelerometer;

a capacitor configured to receive an accelerometer response signal and output a coupled response signal;

a second band pass filter configured to receive, and reduce noise in, the coupled response signal and output a filtered response signal; and

a second amplifier configured to receive the filtered response signal, amplify the filtered response signal, and output a modified accelerometer response signal;

data acquisition circuitry configured to receive the modified accelerometer response signal from the SDA circuitry responsive to the diagnostic signal;

memory storing one or more cross correlation algorithms that diagnose accelerometer health, an attachment condition, or both; and

at least one processor configured to execute the one or more cross correlation algorithms, wherein the at least one processor is configured to;

process a response signal from the data acquisition circuitry using the one or more cross correlation algorithms, and

output an indication of accelerometer health, an attachment condition, or both.

14. The FPGA of claim 13, wherein the FPGA and SDA circuitry are configured to analyze the accelerometer health, the attachment condition, or both, in real time.

15. The FPGA of claim 13, wherein the diagnostic signal is a sinusoidal wave signal that sweeps from approximately 30 kHz to approximately 80 kHz.