Touch sensor pattern

• US 10,073,563 B2
• Filed: 07/26/2016
• Issued: 09/11/2018
• Est. Priority Date: 02/23/2012
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Wilson, Cole D., Prendergast, Patrick N, Peterson, Jonathan R
• Primary Examiner(s): Sasinowski, Andrew
• Application Number:
  US15/219,608
• Publication Number:
  US 20170017347A1
• Time in Patent Office: 777 Days
• CPC Class Codes: G06F 2203/04103 Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
• CPC Class Codes: G06F 2203/04111 Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate
• CPC Class Codes: G06F 3/0418 for error correction or compensation, e.g. based on parallax, calibration or alignment
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
• CPC Class Codes: G06F 3/0448 Details of the electrode shape, e.g. for enhancing the detection of touches, for generating specific electric field shapes, for enhancing display quality

Abstract

An electronic system includes a processing device and a trellis pattern of conductors coupled to the processing device. The trellis pattern of conductors forms a multiple capacitors and the processing device is configured to sense a capacitance of each of the capacitors. A host is coupled to the processing device. The host includes decision logic to determine a state of the trellis pattern of conductors responsive to a signal that indicates a capacitance of one or more capacitors sensed by the processing device.

Claims

1. An electronic system comprising:

a trellis pattern of conductors, wherein the trellis pattern of conductors forms a plurality of capacitors, the trellis pattern of conductors comprises a plurality of unit cells, and an area of a first conductor of the trellis pattern of conductors in each unit cell of the plurality of unit cells is greater than an area of a second conductor of the trellis pattern of conductors within each unit cell of the plurality of unit cells;

a processing device, wherein the trellis pattern of conductors is coupled to the processing device, and the processing device is configured to sense a capacitance of each capacitor of the plurality of capacitors; and

a host coupled to the processing device, the host including decision logic to determine a state of the trellis pattern of conductors responsive to a signal that indicates a capacitance, of at least one of the plurality of capacitors, sensed by the processing device.

2. The electronic system of claim 1, wherein the processing device comprises a network processor having multiple processors including a core unit and multiple micro-engines.

3. The electronic system of claim 1, wherein the host includes a high-level Application Programming Interface used to perform the routine to compensate for the difference in sensitivity to the conductive object among the at least two capacitors of the plurality of capacitors.

4. The electronic system of claim 1, wherein the decision logic is configured to determine that an object is on or in proximity to the trellis pattern of conductors.

5. The electronic system of claim 1, wherein each capacitor of the plurality of capacitors includes one sensor element, of the trellis pattern of conductors, capacitively coupled to another sensor element, of the trellis pattern of conductors.

6. The electronic system of claim 1, wherein the first conductor in each unit cell comprises a main trace and a primary subtrace protruding at a first angle from the main trace.

7. The electronic system of claim 6, wherein the first conductor in each unit cell further comprises a secondary subtrace protruding at a second angle from the primary subtrace.

8. The electronic system of claim 7, wherein the first conductor in each unit cell further comprises a tertiary subtrace protruding at a third angle from the secondary subtrace.

9. The electronic system of claim 7, wherein the second angle is a right angle.

10. The electronic system of claim 8, wherein the third angle is a right angle.

11. The electronic system of claim 6, wherein the first angle is a right angle.