Recovery from programming failure in non-volatile memory

• US 10,073,634 B2
• Filed: 08/07/2015
• Issued: 09/11/2018
• Est. Priority Date: 10/08/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Ojalvo, Shai, Gurgi, Eyal, Kasorla, Yoav
• Primary Examiner(s): Kerveros, Demetrios C
• Application Number:
  US14/821,008
• Publication Number:
  US 20150355858A1
• Time in Patent Office: 1,131 Days
• Field of Search: 714764
• CPC Class Codes: G06F 11/008 Reliability or availability analysis
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A method includes storing data encoded with an Error Correction Code (ECC) in analog memory cells, by buffering the data in a volatile buffer and then writing the buffered data to the analog memory cells while overwriting at least some of the data in the volatile buffer with success indications. Upon detecting a failure in writing the buffered data to the analog memory cells, recovered data is produced by reading both the volatile buffer and the analog memory cells, assigning reliability metrics to respective bits of the recovered data depending on whether the bits were read from the volatile buffer or from the analog memory cells, and applying ECC decoding to the recovered data using the reliability metrics. The recovered data is re-programmed.

Claims

1. An apparatus, comprising:

a buffer memory;

a plurality of memory devices; and

a controller configured to;

receive a page of data for storage;

store the page of data in the buffer memory to generate a buffered data page;

program the page of data in at least one memory device of the plurality of memory devices;

store, based on successful programming of a given data bit included in the page of data, a particular logic value in a respective data bit of a plurality of data bits in the buffer memory;

check the buffer memory to determine if programming the page of data was successful;

retrieve previously programmed data from the at least one memory device in response to a determination that programming the page of data was unsuccessful;

combine the previously programmed data with the buffered data page to generate a combined page;

decode an Error Correction Code (ECC) associated with the combined page to generate a recovered page; and

program the recovered page in the at least one memory device.

2. The apparatus of claim 1, wherein to combine the previously programmed data with the buffered data page, the controller is further configured to assign a respective reliability metric to each data bit of the combined page.

3. The apparatus of claim 2, wherein to assign a respective reliability metric to each data bit of the combined page, the controller is further configured to assign a high reliability metric to a given bit in response to a determination the given bit was retrieved from the buffered data page and that the page of data corresponds to a Least-Significant-Bit (LSB) page.

4. The apparatus of claim 2, wherein to assign a respective reliability metric to each data bit of the combined page, the controller is further configured to assign a high reliability metric to a given bit pair in response to a determination the given bit pair was retrieved from the buffered data page and that the page of data corresponds to a Most-Significant-Bit (MSB) page.

5. The apparatus of claim 1, wherein the particular logic value comprises a logic 1value.

6. The apparatus of claim 1, wherein each memory device of the plurality of memory devices includes a non-volatile memory.

7. A method, comprising:

receiving a page of data for storage;

storing the page of data in a buffer memory to generate a buffered data page;

programming the page of data in at least one memory device of a plurality of memory devices;

storing, based on successful programming of a given data bit included in the page of data, a particular logic value in a respective data bit of a plurality of data bits in the buffer memory;

checking the buffer memory to determine if programming the page of data was successful;

retrieving previously programmed data from the at least one memory device in response to a determination that programming the page of data was unsuccessful;

combining the previously programmed data with the buffered data page to generate a combined page;

decoding an Error Correction Code (ECC) associated with the combined page to generate a recovered page; and

programming the recovered page in the at least one memory device.

8. The method of claim 7, wherein combining the previously programmed data with the buffered data page comprises assigning a respective reliability metric to each data bit of the combined page.

9. The method of claim 8, wherein assigning a respective reliability metric to each data bit of the combined page comprises assigning a high reliability metric to a given bit in response to determining the given bit was retrieved from the buffered data page and that the page of data corresponds to a Least-Significant-Bit (LSB) page.

10. The method of claim 8, wherein assigning a respective reliability metric to each data bit of the combined page comprises assigning a high reliability metric to a given bit pair in response to determining the given bit pair was retrieved from the buffered data page and that the page of data corresponds to a Most-Significant-Bit (MSB) page.

11. The method of claim 8, wherein the respective reliability metric includes a Log-Likelihood Ratio (LLR).

12. The method of claim 7, wherein the particular logic value comprises a logic 1 value.

13. The method of claim 7, further comprising sending an acknowledgement message to a host in response to determining the page of data was successfully programmed.

14. A system, comprising:

a host; and

a storage device that includes a buffer memory and a plurality of memory devices,

wherein the storage device is configured to;

receive a page of data for storage from the host;

store the page of data in the buffer memory to generate a buffered data page;

program the page of data in at least one memory device of the plurality of memory devices;

store, based on successful programming of a respective data bit included in the page of data, a particular logic value in a respective data bit of a plurality of data bits in the buffer memory;

check the buffer memory to determine if programming the page of data was successful;

retrieve previously programmed data from the at least one memory device in response to a determination that programming the page of data was unsuccessful;

combine the previously programmed data with the buffered data page to generate a combined page;

decode an Error Correction Code (ECC) associated with the combined page to generate a recovered page; and

program the recovered page in the at least one memory device.

15. The system of claim 14, wherein to combine the previously programmed data with the buffered data page, the storage device is further configured to assign a respective reliability metric to each data bit of the combined page.

16. The system of claim 15, wherein to assign a respective reliability metric to each data bit of the combined page, the storage device is further configured to assign a high reliability metric to a given bit in response to a determination the given bit was retrieved from the buffered data page and that the page of data corresponds to a Least-Significant-Bit (LSB) page.

17. The system of claim 15, wherein to assign a respective reliability metric to each data bit of the combined page, the storage device is further configured to assign a high reliability metric to a given bit pair in response to a determination the given bit pair was retrieved from the buffered data page and that the page of data corresponds to a Most-Significant-Bit (MSB) page.

18. The system of claim 14, wherein the particular logic value comprises a logic 1 value.

19. The system of claim 14, wherein the storage device is further configured to send an acknowledgement message to a host in response to a determination that the page of data was successfully programmed.

20. The system of claim 14, wherein each memory device of the plurality of memory devices includes a non-volatile memory.