Handling unaligned load operations in a multi-slice computer processor
First Claim
1. A method of handling unaligned load operations in a multi-slice computer processor, the method comprising:
- receiving a request to load data stored within a range of addresses;
determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice;
issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses;
executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice;
receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each of the plurality of data communications busses is associated with one of the distinct processor slices; and
assembling, from the execution results from each distinct processor slice, the data stored within the range of addresses, including;
identifying a portion of each execution result that includes data stored within the range of addresses; and
combining the portion of each execution result that includes data stored within the range into a single result.
1 Assignment
0 Petitions
Accused Products
Abstract
Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.
12 Citations
5 Claims
-
1. A method of handling unaligned load operations in a multi-slice computer processor, the method comprising:
-
receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each of the plurality of data communications busses is associated with one of the distinct processor slices; and assembling, from the execution results from each distinct processor slice, the data stored within the range of addresses, including;
identifying a portion of each execution result that includes data stored within the range of addresses; andcombining the portion of each execution result that includes data stored within the range into a single result. - View Dependent Claims (2, 3, 4, 5)
-
Specification