Seeding mechanism for error detection codes

• US 10,073,735 B1
• Filed: 10/28/2014
• Issued: 09/11/2018
• Est. Priority Date: 10/28/2014
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Cai, Jun, Kella, Jeetandra, Ong, ChuanPeng, Edgar, Brian T
• Primary Examiner(s): Lamarre, Guy
• Application Number:
  US14/526,184
• Time in Patent Office: 1,414 Days
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature

Abstract

Systems and methods are disclosed for a seeding mechanism for error detection codes. An error detection code may be generated using specifically modified seed input and stored to data sectors not containing valid data. A data storage device may determine if read attempts are directed to an invalid sector by analysis of the stored error detection code. In some embodiments, an apparatus may determine a first error detection code stored to a target data storage sector does not match a second error detection code calculated for the target data storage sector, compare the first error detection code to a modified error code value to determine whether the target data storage sector contains valid data, and return an indication that the target data storage sector does not contain valid data when the error detection code matches the modified error code value.

Claims

1. An apparatus comprising:

a processor configured to;

calculate and record EDC values for memory locations containing valid data based on a first set of seed values to an EDC function; and

calculate and record alternate EDC values for memory locations containing invalid data based on a second set of seed values to the EDC function;

the first set of seed values includes a first logical block address (LBA) value associated with the respective memory location containing valid data;

the second set of seed values includes a different LBA value than a second LBA value associated with the respective memory location containing invalid data;

calculate a modified EDC based on the second set of seed values;

compare a first error detection code (EDC) stored to a target memory location to the modified EDC to determine whether the target memory location contains valid data; and

return an indication that the target memory location does not contain valid data when the first EDC matches the modified EDC.

2. The apparatus of claim 1 comprising the processor further configured to:

sequentially read data sectors from a band of tracks recorded in a shingled manner; and

designate a second memory location preceding the target memory location as a last valid memory location in the band when the first EDC of the target memory location matches the modified EDC.

3. The apparatus of claim 1 comprising the processor further configured to:

receive a read command from a host device directed to the target memory location;

generate a default bit pattern to return to the host when the first EDC matches the modified EDC; and

return the default bit pattern to the host.

4. The apparatus of claim 1 further comprising:

the different LBA value includes a one'"'"'s complement of the second LBA value.

5. The apparatus of claim 1 further comprising:

the different LBA value includes a specific LBA value designated for use in the second set of seed values.

6. The apparatus of claim 1 comprising the processor further configured to:

compare the first EDC to a comparison EDC calculated using the first set of seed values;

determine that the target memory location contains valid data when the first EDC matches the comparison EDC;

compare the first EDC to the modified EDC when the first EDC does not match the comparison EDC; and

determine a read error when the first EDC does not match the modified EDC.

7. The apparatus of claim 1 comprising the processor further configured to:

receive a read command directed to the target memory location in a first physical band of tracks recorded in a shingled manner;

calculate a comparison EDC based on a first logical block address (LBA) currently associated with the target memory location;

compare the first EDC with the comparison EDC;

determine that the target memory location contains valid data when the first EDC matches the comparison EDC; and

calculate the modified EDC based on a second LBA previously associated with the target memory location.

8. The apparatus of claim 7 comprising the processor further configured to:

receive a write command directed to a range of LBAs associated with a second physical band of tracks recorded in a shingled manner;

read valid data from the second physical band and modify the valid data to include data associated with the write command to create modified data;

write the modified data to the first physical band of tracks, the first physical band having invalid data and recorded EDC values generated based on LBAs associated with the invalid data; and

associate the range of LBAs with the first physical band.

9. A method comprising:

calculating and recording EDC values for memory locations containing valid data based on a first set of seed values to an EDC function;

calculating and recording alternate EDC values for memory locations containing invalid data based on a second set of seed values to the EDC function;

receiving a request to read a target memory location of a data storage device;

calculating a modified EDC based on the second set of seed values;

comparing a first error detection code (EDC) stored to the target memory location to the modified EDC to determine whether the target memory location contains valid data; and

returning an indication that the target memory location does not contain valid data when the first EDC matches the modified EDC.

10. The method of claim 9 further comprising:

sequentially reading data sectors from a band of tracks recorded in a shingled manner; and

designating a second memory location preceding the target memory location as a last valid memory location in the band when the first EDC of the target memory location matches the modified EDC.

11. The method of claim 9 further comprising:

the first set of seed values includes a first logical block address (LBA) value associated with the memory location containing the valid data; and

the second set of seed values includes a different LBA value than a second LBA value associated with the memory location containing the invalid data.

12. The method of claim 11 further comprising:

comparing the first EDC to a comparison EDC calculated using the first set of seed values;

determining that the target memory location contains valid data when the first EDC matches the comparison EDC;

comparing the first EDC to the modified EDC when the first EDC does not match the comparison EDC; and

determining a read error when the first EDC does not match the modified EDC.

13. The method of claim 9 further comprising:

receiving the request directed to the target memory location in a first physical band of tracks recorded in a shingled manner;

calculating a comparison EDC based on a first logical block address (LBA) currently associated with the target memory location;

comparing the first EDC with the comparison EDC;

determining that the target memory location contains valid data when the first EDC matches the comparison EDC; and

calculating the modified EDC based on a second LBA previously associated with the target memory location.

14. The method of claim 13 further comprising:

receiving a write command directed to a range of LBAs associated with a second physical band of tracks recorded in a shingled manner;

reading valid data from the second physical band of tracks and modify the valid data to include data associated with the write command to create modified data;

writing the modified data to the first physical band of tracks, the first physical band of tracks having invalid data and recorded EDC values generated based on LBAs associated with the invalid data; and

associating the range of LBAs with the first physical band.

15. A memory device that stores instructions that, when executed, cause a processor to perform a method comprising:

calculating and recording EDC values for memory locations containing valid data based on a first set of seed values to an EDC function, the first set of seed values including a first logical block address (LBA) value associated with the respective memory location containing valid data; and

calculating and recording alternate EDC values for memory locations containing invalid data based on a second set of seed values to the EDC function, the second set of seed values including includes a different LBA value than a second LBA value associated with the respective memory location containing invalid data;

receiving a request to read a target memory location of a data storage device;

calculating a modified EDC based on the second set of seed values;

comparing a first error detection code (EDC) stored to the target memory location to the modified EDC to determine whether the target memory location contains valid data; and

determining the target memory location does not contain valid data when the first EDC matches the modified EDC.

16. The memory device of claim 15, the method further comprising:

calculating a comparison EDC based on a first logical block address (LBA) currently associated with the target memory location;

comparing the first EDC with the comparison EDC;

determining that the target memory location contains valid data when the first EDC matches the comparison EDC; and

calculating the modified EDC based on a second LBA previously associated with the target memory location.

17. The memory device of claim 15 further comprising:

the different LBA value includes a one'"'"'s complement of the second LBA value.

18. The memory device of claim 15 further comprising:

the different LBA value includes a specific LBA value designated for use in the second set of seed values.

19. The memory device of claim 15 comprising the method further configured to:

comparing the first EDC to a comparison EDC calculated using the first set of seed values;

determining that the target memory location contains valid data when the first EDC matches the comparison EDC;

comparing the first EDC to the modified EDC when the first EDC does not match the comparison EDC; and

determining a read error when the first EDC does not match the modified EDC.