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Universal smart connection pad

  • US 10,073,752 B2
  • Filed: 01/13/2016
  • Issued: 09/11/2018
  • Est. Priority Date: 01/13/2016
  • Status: Active Grant
First Claim
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1. A system, comprising:

  • a) a processing system that includes a processor;

    b) a connection pad, which includes(i) a set of pins, which(A) are arranged equally-spaced in a grid having a plurality of rows and a plurality of columns,(B) have magnetic polarities that alternate within a row in the plurality of rows, and alternate within a column in the plurality of columns,(C) are equally-spaced within a row in the plurality of rows, and equally-spaced within a column in the plurality of column, and(D) through a first subset of which the connection pad can electronically connect to a first slave device and communicate electronically with the first slave device,(ii) a first hardware interface through which the pad can electrically connect to a host device and communicate electronically with the host device, andc) the host device, which includes a second hardware interface through which the host device can electrically connect to the connection pad and communicate electronically with the connection pad,d) connection management logic, which includes(i) a power module, under control of the processing system, whereby the host device provides power through a first subset of pins in the set of pins, to the first slave device, which is external to the host device,(ii) a mating module, under control of the processing system, whereby the host device receives identification information from the first slave device and establishes and maintains electronic data communication with the first slave device through a second subset of pins in the set of pins, and the first and the second hardware interfaces, and(iii) a pin assignment module, under control of the processing system, whereby the host device transmits pin assignment information to the first slave device through a third subset of pins in the set of pins, and the first and the second hardware interfaces, wherein the first, second, and third subsets of pins are not necessarily pairwise mutually exclusive.

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