Processors having virtually clustered cores and cache slices
First Claim
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1. A processor comprising:
- a plurality of logical processors each having one or more corresponding lower level caches;
a shared higher level cache that is to be shared by the plurality of logical processors, in which the shared higher level cache includes a physically distributed cache slice that is physically distributed across a die for each of the plurality of logical processors, wherein the physically distributed cache slices are physically separated from one another on the die; and
logic to direct a missed access in one or more lower level caches of a corresponding given logical processor initially to only a first subset of the physically distributed cache slices of the shared higher level cache of a first virtual cluster that includes at least two of the plurality of logical processors including the given logical processor, wherein the first virtual cluster does not include a second subset of the physically distributed cache slices of the shared higher level cache that are included in a second virtual cluster that includes at least two of the plurality of logical processors.
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Abstract
A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.
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Citations
21 Claims
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1. A processor comprising:
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a plurality of logical processors each having one or more corresponding lower level caches; a shared higher level cache that is to be shared by the plurality of logical processors, in which the shared higher level cache includes a physically distributed cache slice that is physically distributed across a die for each of the plurality of logical processors, wherein the physically distributed cache slices are physically separated from one another on the die; and logic to direct a missed access in one or more lower level caches of a corresponding given logical processor initially to only a first subset of the physically distributed cache slices of the shared higher level cache of a first virtual cluster that includes at least two of the plurality of logical processors including the given logical processor, wherein the first virtual cluster does not include a second subset of the physically distributed cache slices of the shared higher level cache that are included in a second virtual cluster that includes at least two of the plurality of logical processors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method comprising:
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virtually clustering a first plurality of logical processors, including a given logical processor, into a first virtual cluster; virtually clustering a second plurality of logical processors into a second virtual cluster, in which each of the first and second pluralities of logical processors has one or more corresponding lower level caches; and directing an access that misses in one or more lower level caches corresponding to the given logical processor initially to only a first subset of physically distributed cache slices, of a shared higher level cache, that are in the first virtual cluster that corresponds to the given logical processor, wherein the first virtual cluster does not include a second subset of the physically distributed cache slices, of the shared higher level cache, that correspond to the second virtual cluster, and wherein each of the physically distributed cache slices in the first subset is physically co-located on a die with a different one of the first plurality of logical processors, and each of the physically distributed cache slices in the second subset is physically co-located on the die with a different one of the second plurality of logical processors. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21)
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Specification