Apparatuses and methods for compute enabled cache

• US 10,073,786 B2
• Filed: 03/10/2016
• Issued: 09/11/2018
• Est. Priority Date: 05/28/2015
• Status: Active Grant

• Current Assignee: Lodestar Licensing Group LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Murphy, Richard C.
• Primary Examiner(s): Bui, Tha-O H
• Application Number:
  US15/066,488
• Publication Number:
  US 20160350230A1
• Time in Patent Office: 915 Days
• Field of Search: 365149
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 2212/1012 Design facilitation
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/6032 Way prediction in set-associative cache
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present application includes apparatuses and methods for compute enabled cache. An example apparatus includes a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.

Claims

1. An apparatus, comprising:

a memory configured to store cache data and having;

a memory array;

a sensing circuitry comprising a plurality of sense amplifiers and a plurality of compute components to perform logical operations; and

a memory controller coupled to the memory array, the memory controller configured to;

create a block select as metadata to a cache line to control alignment of cache blocks within the memory array; and

create a subrow select as metadata to the cache line to control placement of the cache line on a particular row in the memory array to align the cache line to one or more of the plurality of compute components.

2. The apparatus of claim 1, wherein the memory is a last layer cache (LLC) memory.

3. The apparatus of claim 2, wherein the plurality of compute components are configured to access and to operate on cached data in the LLC memory without moving the cached data to a higher level in the memory.

4. The apparatus of claim 1, wherein the plurality of compute components are a static random access memory (SRAM) logic resource integrated with the memory array of the memory.

5. The apparatus of claim 1, wherein:

the block select enables an offset to the cache line; and

the subrow select enables multiple sets to a set associative cache.

6. The apparatus of claim 1, wherein the block select provides an offset to a page in a dynamic random access memory (DRAM) page.

7. The apparatus of claim 1, wherein the block select and the subrow select are not part of an address space of a host processor.

8. The apparatus of claim 7, wherein the memory controller is configured to:

change the block select and the subrow select; and

relocate the cached data transparently to the host processor.

9. The apparatus of claim 8, wherein the memory controller is configured to store a copy of the block select and the subrow select internal to the host processor.

10. The apparatus of claim 1, wherein the block select controls alignment of cache blocks within the memory array.

11. The apparatus of claim 10, wherein the memory array is a static random access memory (SRAM) array on a logic resource of a host.

12. The apparatus of claim 10, wherein the memory array is a dynamic random access memory (DRAM) array on a processing in memory (PIM) device.

13. The apparatus of claim 1, wherein the subrow select controls placement of the cache line on multiple different rows in the memory array in the memory.

14. The apparatus of claim 13, wherein:

the subrow select is four (4) bits to allow a selection of 1 of 16 rows of the memory array for a given cache block; and

the subrow select is added to a portion of a tag in the cache line.

15. The apparatus of claim 1, wherein the memory controller is configured to:

use the block select to control alignment of cached data in the memory array in the memory; and

use the subrow select to control resource allocation in the memory array.

16. The apparatus of claim 15, wherein the cache memory controller is configured to:

use the block select to choose which part of a row in the memory array having a first bit width to access as a chunk having a second bit width as part of an array access request;

use the block select and the subrow select in a repeated manner to allow a cache line to be split and placed differently in a bank of dynamic random access memory (DRAM).

17. The apparatus of claim 16, wherein:

the memory array is in a processing in memory (PIM) based device;

at least a portion of the cache line is handled as a vector having four (4) third bit length bit values; and

a plurality of different cache blocks are placed in a plurality of different banks in a dynamic random access memory (DRAM) to allow multiple mapped single cache lines.

18. The apparatus of claim 17, wherein the memory controller is configured to manage a first bit length cache line on a second bit length interface such that four (4) second bit length chunks can each have a different alignment.

19. An apparatus, comprising:

a memory device configured to couple to a host, wherein the memory device includes;

an array of memory cells;

sensing circuitry coupled to the array, the sensing circuitry including a plurality of sense amplifiers and a plurality of compute components configured to perform logical operations; and

a memory controller coupled to the array and sensing circuitry, the memory controller configured to;

receive a cache line having block select and subrow select metadata; and

operate on the block select and subrow select metadata to;

control alignment of cache blocks in the array; and

allow the cache line to be placed on a particular row of the array to align the cache line to one or more of the plurality of compute components.

20. The apparatus of claim 19, wherein the apparatus further includes a cache controller to:

create the block select metadata and insert to the cache line; and

create the subrow select metadata and insert to the cache line.

21. The apparatus of claim 20, wherein the cache controller is located on the memory device.

22. The apparatus of claim 20, wherein the cache controller is located off-package on the host and coupled to the memory device.

23. The apparatus of claim 19, wherein the memory controller is configured to:

operate on the cache line to control alignment of cache blocks in the array according to the block select metadata; and

operate on the cache line to allow the cache line to be placed on multiple different rows to the array according to the row select metadata.

24. The apparatus of claim 19, wherein the block select metadata and the row select metadata are stored internal to the memory device and are transparent to an address space of a processing resource of the host.

25. The apparatus of claim 19, wherein each cache line is handled as multiple vectors of different bit length values.

26. The apparatus of claim 25, wherein each of the different bit length values of the multiple vectors is further subdived into multiple elements.

27. The apparatus of claim 26, wherein the memory controller is configured to use the subrow select metadata to select a subarray to place an element of the multiple elements of a vector.

28. The apparatus of claim 25, wherein the memory controller is configured to handle each vector of the multiple vectors as a chunk.

29. The apparatus of claim 19, wherein the memory controller is configured to:

store the cache block in the array; and

retrieve a cache line to perform logical operations with the plurality of compute components.

30. The apparatus of claim 19, wherein the array of memory cells are dynamic random access memory (DRAM) cells.

31. The apparatus of claim 30, wherein the memory controller is configured to use a DRAM protocol and DRAM logical and electrical interfaces to receive the cache line and to retrieve the cache line to perform logical operations with the plurality of compute components.

32. An apparatus, comprising:

a processing resource;

a memory having;

a memory array coupled to the processing resource;

a sensing circuitry comprising a plurality of sense amplifiers and a plurality of compute components to perform logical operations; and

wherein at least one of the processing resource or the memory has a memory controller associated therewith, wherein, the memory controller is configured to;

create a block select as metadata to a cache line to control alignment of cache blocks within the memory array; and

create a subrow select as metadata to the cache line to control placement of the cache line on a particular row in the memory array to align the cache line to one or more of the plurality of compute components; and

an interface between the processing resource and the memory.

33. The apparatus of claim 32, wherein the processing resource comprises a static random access memory (SRAM) and the memory controller is configured to store the block select and the subrow select in the SRAM.

34. The apparatus of claim 32, wherein the interface comprises through silicon vias (TSVs) coupling the processing resource to the memory.

35. The apparatus of claim 34, wherein the apparatus is a 3D integrated logic/memory.

36. The apparatus of claim 32, wherein the memory is a processing in memory (PIM) device, the memory array is a dynamic random access memory (DRAM) array, and wherein the PIM device includes:

the sensing circuitry coupled to the memory array, the sensing circuitry including the plurality of sense amplifiers and the plurality of compute components configured to perform logical operations; and

wherein the memory controller is coupled to the memory array and the sensing circuitry, the memory controller configured to;

receive the cache line having block select and subrow select metadata from the processing resource; and

operate on the block select and subrow select metadata to;

control alignment of a cache block in the memory array; and

control placement of the cache line on a particular row of the memory array.

37. The apparatus of claim 36, wherein the memory controller is configured to:

operate on the cache line to control alignment of the cache block in the memory array according to the block select metadata; and

operate on the cache line to allow the cache line to be placed on multiple different rows to the memory array according to the row select metadata.

38. The apparatus of claim 36, wherein each cache line is handled as multiple vectors, the cache block is a vector, the vector is a plurality of defined bit length values, and wherein each of the plurality of defined bit length values is an element usable in a logical operation.

39. The apparatus of claim 38, wherein the memory controller is configured to use the subrow select metadata to select a subarray to store an element of the cache line.

40. The apparatus of claim 38, wherein the memory controller is configured to:

store the cache block in the memory array; and

retrieve an element of the cache line to perform logical operations with the plurality of compute components.

41. The apparatus of claim 36, wherein the memory controller is configured to control the sensing circuitry to perform logical operations including AND, OR, NOT, XOR, NAND, and NOR logical operations.

42. A method for operating a cache memory, comprising:

creating a block select as metadata to a cache line to control alignment of cache blocks in a memory array of the cache memory comprising sensing circuitry including a plurality of sense amplifiers and a plurality of compute components to perform logical operations; and

creating a subrow select as metadata to the cache line to control placement of at least a portion of the cache line on a particular row in the memory array to align the portion of the cache line to one or more of the plurality of compute components.

43. The method of claim 42, wherein the method comprises:

receiving the block select and the subrow select to the memory controller in a processing in memory (PIM) device, the memory array is a dynamic random access memory (DRAM) array, wherein the PIM device comprises;

the sensing circuitry coupled to the memory array, the sensing circuitry including the plurality of sense amplifiers and the plurality of compute components configured to implement logical operations;

storing the cache block in the memory array; and

retrieving at least a portion of the cache line to perform logical operations with the plurality of compute components.

44. The method of claim 43, wherein storing the cache block in the memory array comprises storing a portion of a cache block having a bit length that is less than a bit length of the cache line.