Electronic system with memory management mechanism and method of operation thereof

• US 10,073,790 B2
• Filed: 02/26/2018
• Issued: 09/11/2018
• Est. Priority Date: 12/03/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Malladi, Krishna T., Zheng, Hongzhong
• Primary Examiner(s): Nguyen, Hien
• Application Number:
  US15/905,348
• Publication Number:
  US 20180181494A1
• Time in Patent Office: 197 Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0884 Parallel mode, e.g. in parallel with main memory or CPU
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 2212/6046 Using a specific cache allocation policy other than replacement policy
• CPC Class Codes: G06F 3/0611 in relation to response time

Abstract

An electronic system includes: a processor configured to access operation data; a high speed local memory, coupled to the processor, configured to store a limited amount of the operation data; and a memory subsystem, coupled to the high speed local memory, including: a module memory controller configured to access the operational data for the processor and the high speed local memory, a local cache controller, coupled to the module memory controller, including a fast control bus configured to store the operation data, with critical timing in a first tier memory, and a memory tier controller, coupled to the local cache controller, including a reduced performance control bus configured to store the operation data with non-critical timing in a second tier memory.

Claims

1. An electronic system comprising:

a processor configured to access operation data;

a high speed local memory, coupled to the processor, configured to store a limited amount of the operation data; and

a memory subsystem, coupled to the high speed local memory, including;

a module memory controller configured to access the operational data for the processor and the high speed local memory,

a local cache controller, coupled to the module memory controller, including a fast control bus configured to store the operation data, with critical timing in a first tier memory, and

a memory tier controller, coupled to the local cache controller, including a reduced performance control bus configured to store the operation data with non-critical timing in a second tier memory.

2. The system as claimed in claim 1 wherein the second tier memory provides more capacity and longer latency than the first tier memory.

3. The system as claimed in claim 1 wherein the second tier memory includes a modified local bit-line sense amplifier having a bit-line feedback circuit.

4. The system as claimed in claim 1 wherein the second tier memory includes a global word-line driver coupled to a storage cell array.

5. The system as claimed in claim 1 wherein the second tier memory includes a storage cell array with a poly-silicon interconnect for a bit-line (BL).

6. The system as claimed in claim 1 wherein the memory subsystem is configured to provide the first tier memory as a hardware cache to the second tier memory.

7. The system as claimed in claim 1 wherein the memory subsystem is configured to provide a software tiering mechanism between the first tier memory and the second tier memory.

8. The system as claimed in claim 1 wherein the memory subsystem is configured to provide a remote software tiering mechanism between the first tier memory, coupled to the processor, and the second tier memory, coupled to a remote processor.

9. The system as claimed in claim 1 wherein the memory subsystem is configured to provide an integrated memory including the first tier memory and the second tier memory.

10. The system as claimed in claim 1 further comprising an interface adapter, between the first tier memory, accessed by the processor, and the second tier memory, accessed by a remote processor, for providing a remote software tiering mechanism.

11. An method of operation of an electronic system comprising:

accessing operation data by a processor;

storing a limited amount of the operation data in a high speed local memory;

accessing the operational data for the processor and the high speed local memory through a module memory controller;

storing the operation data, with critical timing, in a first tier memory by a local cache controller; and

storing the operation data, with non-critical timing, in a second tier memory by loading the operational data through the local cache controller to a memory tier controller for accessing the second tier memory.

12. The method as claimed in claim 11 further comprising configuring the first tier memory as a hardware cache to the second tier memory.

13. The method as claimed in claim 11 further comprising configuring a software tiering mechanism between the first tier memory and the second tier memory managed by the processor.

14. The method as claimed in claim 11 further comprising configuring a remote software tiering mechanism between the first tier memory, coupled to the processor, and the second tier memory, coupled to a remote processor.

15. The method as claimed in claim 11 further comprising providing an integrated memory by accessing the second tier memory and an extension of the first tier memory including controlling the integrated memory through the module memory controller.

16. The method as claimed in claim 11 further comprising providing a remote software tiering mechanism by accessing an interface adapter between the first tier memory, accessed by the processor, and the second tier memory, accessed by a remote processor.