Methods, systems, and computer program product for implementing synchronous clones for an electronic design

• US 10,073,942 B1
• Filed: 09/30/2016
• Issued: 09/11/2018
• Est. Priority Date: 09/30/2016
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Ginetti, Arnold
• Primary Examiner(s): Lin, Sun
• Application Number:
  US15/282,778
• Time in Patent Office: 711 Days
• Field of Search: 716100, 716119
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed are methods, systems, and articles of manufacture for implementing clones for an electronic design. These methods and systems identify a schematic design of an electronic design and a set of cloning rules, configurations, or settings for implementing clones for the electronic design. These methods and systems then generate a plurality of synchronous clones in a layout of the electronic design based in part or in whole upon the set of cloning rules, configurations, or settings, without parsing the electronic design or a portion thereof.

Claims

1. A computer-implemented method for implementing clones for an electronic design, the computer implemented method comprising:

identifying a schematic design of an electronic design;

identifying a set of cloning rules, configurations, or settings; and

generating a plurality of synchronous clones of a cloning source device for a plurality of layout circuit component designs in a layout of the electronic design based in part or in whole upon the set of cloning rules, configurations, or settings, without parsing the electronic design or a portion thereof to determine whether the plurality of layout circuit component designs match the cloning source device.

2. The computer-implemented method of claim 1, further comprising:

identifying a schematic circuit component design from the schematic design corresponding to the layout of the electronic design;

identifying schematic hierarchy information of the schematic circuit component design in the schematic design; and

determining whether the layout includes the plurality of layout circuit component designs bound to the schematic circuit component design.

3. The computer-implemented method of claim 2, further comprising:

updating a synchronous clone data structure with first information about the plurality of layout circuit component designs, second information about the schematic hierarchy, or third information about the schematic circuit component design.

4. The computer-implemented method of claim 2, further comprising at least one of:

creating a figure group for a synchronous clone for a layout circuit component design of the plurality of layout circuit component designs;

placing a plurality of geometric shapes in the figure group;

materializing the figure group comprising the plurality of geometric shapes that have been placed into a materialized cell or a materialized block;

materializing a virtual hierarchy at which the figure group is located into a physical hierarchy;

updating a physical hierarchical structure of the layout with at least the physical hierarchy corresponding to the virtual hierarchy;

or

performing routing within the materialized cell or the materialized block or between two materialized cells, between two materialized blocks, or between the materialized cell and the materialized block.

5. The computer-implemented method of claim 2, further comprising:

determining whether synchronous clones are to be created for two or more layout circuit component designs of the plurality of layout circuit component designs.

6. The computer-implemented method of claim 5, wherein the act of determining whether the synchronous clones are to be created further comprising:

identifying first layout instances corresponding to the schematic circuit component design; and

determining whether at least two first layout instances of the first layout instances correspond to a same topology.

7. The computer-implemented method of claim 6, wherein the act of determining whether the synchronous clones are to be created further comprising:

determining whether the layout is a hierarchical layout including two or more physical hierarchies when at least two first layout instances of the first layout instances are determined to correspond to a same topology.

8. The computer-implemented method of claim 7, wherein the act of determining whether the synchronous clones are to be created further comprising:

identifying a lowest hierarchy from the two or more physical hierarchies at which the at least two first layout instances are located when the layout is determined to be the hierarchical layout; and

traversing one or more parent layout circuit component designs at one or more parent physical hierarchies of the lowest hierarchy when the layout is determined to be the hierarchical layout.

9. The computer-implemented method of claim 7, wherein the act of determining whether the synchronous clones are to be created further comprising:

identifying one or more common hierarchical parameters included in or corresponding to the at least two first layout instances;

determining whether at least one common hierarchical parameter of the one or more common hierarchical parameters is relaxable; and

reducing a search space for determining whether the synchronous clones are to be created at least by discarding the at least one common hierarchical parameter in determining whether the synchronous clones are to be created.

10. The computer-implemented method of claim 9, wherein the act of determining whether the synchronous clones are to be created further comprising:

determining whether parameter values of the at least one common hierarchical parameter for the at least two first layout instances are identical; and

generating at least two synchronous clones based in part or in whole upon whether the parameter values are identical.

11. A system for implementing clones for an electronic design, the system comprising:

non-transitory computer accessible storage medium storing thereupon program code;

at least one processor executing the program code to identify a schematic design of an electronic design; and

one or more modules that are stored at least partially in memory of one or more computing systems, that include or function in conjunction with at least one hardware processor of the one or more computing systems, and that are configured to execute the program code to identify a set of cloning rules, configurations, or settings, wherein

the at least one processor further executing the program code to generate a plurality of synchronous clones of a cloning source device for a plurality of layout circuit component designs in a layout of the electronic design based in part or in whole upon the set of cloning rules, configurations, or settings, without parsing the electronic design or a portion thereof to determine whether the plurality of layout circuit component designs match the cloning source device.

12. The system for claim 11, wherein the at least one processor further executes the program code to identify a schematic circuit component design from the schematic design corresponding to the layout of the electronic design, to identify schematic hierarchy information of the schematic circuit component design in the schematic design, and to determine whether the layout includes a plurality of layout circuit component designs bound to the schematic circuit component design.

13. The system for claim 12, wherein the at least one processor further executes the program code to update a synchronous clone data structure with first information about the plurality of layout circuit component designs, second information about the schematic hierarchy, or third information about the schematic circuit component design.

14. The system for claim 12, wherein the at least one processor further executes the program code at least to create a figure group for a synchronous clone for a layout circuit component design of the plurality of layout circuit component designs, to place a plurality of geometric shapes in the figure group, to materialize the figure group comprising the plurality of geometric shapes that have been placed into a materialized cell or a materialized block, to materialize a virtual hierarchy at which the figure group is located into a physical hierarchy, to update a physical hierarchical structure of the layout with at least the physical hierarchy corresponding to the virtual hierarchy, or to perform routing within the materialized cell or the materialized block or between two materialized cells, between the two materialized blocks, or between the materialized cell and the materialized block.

15. The system for claim 12, wherein the at least one processor further executes the program code to determine whether synchronous clones are to be created for two or more layout circuit component designs of the plurality of layout circuit component designs, to identify first layout instances corresponding to the schematic circuit component design, and to determine whether at least two first layout instances of the first layout instances correspond to a same topology.

16. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a set of acts for implementing clones for an electronic design, the set of acts comprising:

identifying a schematic design of an electronic design;

identifying a set of cloning rules, configurations, or settings;

generating a plurality of synchronous clones of a cloning source device for a plurality of layout circuit component designs in a layout of the electronic design based in part or in whole upon the set of cloning rules, configurations, or settings, without parsing the electronic design or a portion thereof to determine whether the plurality of layout circuit component designs match the cloning source device.

17. The article of manufacture of claim 16, wherein the set of acts further comprises:

identifying a schematic circuit component design from the schematic design corresponding to the layout of the electronic design;

identifying schematic hierarchy information of the schematic circuit component design in the schematic design; and

determining whether the layout includes a plurality of layout circuit component designs bound to the schematic circuit component design.

18. The article of manufacture of claim 17, wherein the set of acts further comprises:

determining whether synchronous clones are to be created for two or more layout circuit component designs of the plurality of layout circuit component designs;

identifying first layout instances corresponding to the schematic circuit component design; and

determining whether at least two first layout instances of the first layout instances correspond to a same topology.

19. The article of manufacture of claim 18, wherein the set of acts further comprises:

identifying one or more common hierarchical parameters included in or corresponding to the at least two first layout instances;

determining whether at least one common hierarchical parameter of the one or more common hierarchical parameters is relaxable; and

reducing a search space for determining whether the synchronous clones are to be created at least by discarding the at least one common hierarchical parameter in determining whether the synchronous clones are to be created.

20. The article of manufacture of claim 19, wherein the set of acts further comprises:

determining whether parameter values of the at least one common hierarchical parameter for the at least two first layout instances are identical; and

generating at least two synchronous clones based in part or in whole upon whether the parameter values are identical.