Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory

• US 10,074,414 B2
• Filed: 08/16/2017
• Issued: 09/11/2018
• Est. Priority Date: 08/31/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Derner, Scott J., Kawamura, Christopher J.
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US15/679,016
• Publication Number:
  US 20180061469A1
• Time in Patent Office: 391 Days
• Field of Search: 365145, 365149, 365117, 365190
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/2257 Word-line or row circuits
• CPC Class Codes: G11C 11/2259 Cell access
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/2275 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/2293 Timing circuits or methods
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: H10B 53/20 characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 53/40 characterised by the peripheral circuit region

Abstract

Apparatuses and methods are disclosed that in ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.

Claims

1. An apparatus, comprising:

a ferroelectric memory cell including first and second selection components;

first and second digit lines coupled to the first and second selection components, respectively;

a first access line coupled to a gate of the first selection component;

a second access line coupled to a gate of the second selection component;

a sense component including a first sense node and a second sense node, the sense component configured to sense a voltage difference between the first and second sense nodes, amplify the voltage difference, and latch the voltage difference;

a first switch coupled to the first digit line and the first sense node, the first switch configured to selectively couple the first digit line to the first sense node responsive to a first control signal;

a second switch coupled to the second digit line and the second sense node, the second swatch coupled to selectively couple the second digit line to the second sense node responsive to a second control signal.

2. The apparatus of claim 1, further comprising a driver circuit configured to provide a read voltage to the first digit line.

3. The apparatus of claim 1 wherein the sense component comprises:

a first p-type field effect transistor having a gate;

a first n-type field effect transistor having a gate coupled to the gate of the first p-type field effect transistor;

a second p-type field effect transistor having a gate; and

a second n-type field effect transistor having a gate coupled to the gate of the second p-type field effect transistor;

wherein the first sense node coupled to drains of the first p-type and first n-type field effect transistors, and further coupled to the gates of the second p-type and second n-type field effect transistors; and

wherein the second sense node coupled to drains of the second p-type and second n-type field effect transistors, and further coupled to the gates of the first p-type and first n-type field effect transistors.

4. The apparatus of claim 3, further comprising:

a plurality of first access lines each coupled to the first selection component of each respective ferroelectric memory cell of a plurality of ferroelectric memory cells, the plurality of ferroelectric memory cells including the ferroelectric memory cell; and

a plurality of second access lines each coupled to the second selection component of each respective ferroelectric memory cell of the plurality of ferroelectric memory cells.

5. The apparatus of claim 1 wherein the ferroelectric memory cell comprises:

a first plate coupled to the first selection component;

a second plate coupled to the second selection component; and

a ferroelectric material positioned between the first and second plates.

6. The apparatus of claim 1, further comprising a reference switch coupled to the first sense node and configured to provide a reference voltage to the first sense node.

7. The apparatus of claim 1, further comprising:

a plurality of ferroelectric memory cells coupled to the first and second digit lines, each of the ferroelectric memory cells of the plurality of ferroelectric memory cells including respective first and second selection components.

8. The apparatus of claim 1 wherein the first and second digit lines are vertically offset relative to one another, and a ferroelectric capacitor vertically between the first and second selection components.

9. An apparatus comprising:

a plurality of memory cells arranged in rows and columns, each memory cell including first and second selection components, and further including a ferroelectric capacitor coupled between the first and second selection components;

a plurality of pairs of word lines, each pair of word lines of the plurality of pairs of word lines coupled to a respective row of memory cells, wherein each pair of word lines coupled to a respective gate of a respective first selection component, and wherein each pair of word lines coupled to a respective gate of a respective second selection component;

a plurality of pairs of digit lines, each pair of digit lines of the plurality of pairs of digit lines coupled to a respective column of memory cells;

a row decoder coupled to the plurality of pairs of word lines and configured to activate a pair of word lines based on a row address;

a column decoder coupled to the plurality of pairs of digit lines and configured to activate a pair of digit lines based on a column address; and

sense components coupled to the plurality of pairs of digit lines and configured to determine the stored states of the memory cells of an activated row of memory cells.

10. The apparatus of claim 9 wherein each of the plurality of pairs of digit lines includes a first digit line coupled to the first selection components of the memory cells of the respective column of memory cells and further includes a second digit line coupled to the second selection components of the memory cells of the respective column of memory cells.

11. The apparatus of claim 10 wherein the sense components comprises a respective sense component coupled to each of the pairs of digit lines of the plurality of digit lines.

12. The apparatus of claim 11 wherein each sense component is configured to drive the second digit line of the pair of digit lines to which the sense component is coupled to a voltage and the sense component is further configured to drive the first digit line of the pair of digit lines to which the sense component is coupled to a voltage complementary to the voltage of the second digit line.

13. The apparatus of claim 10 wherein each pair of word lines of the plurality includes a first word line coupled to gates of the first selection components of the respective row of memory cells and further includes a second word line coupled to gates of the second selection components of the respective row of memory cells, wherein the first selection components of the respective row of memory cells are activated by the first word line and the second selection components of the respective row of memory cells are activated by the second word line.

14. The apparatus of claim 9 wherein the first selection component, second selection component, and ferroelectric capacitor are vertically stacked and the ferroelectric capacitor is vertically between the first and second selection components.

15. A method, comprising:

coupling a first plate of a memory capacitor to a first digit line;

coupling a second plate of the memory capacitor to a second digit line;

providing a read voltage to the first plate of the memory capacitor to cause a change in voltage at the second plate of the memory capacitor;

sensing a voltage difference between a voltage at the second plate of the memory capacitor and a reference voltage;

amplifying the voltage difference to provide an amplified voltage difference;

applying the amplified voltage difference to the first and second plates of the memory capacitor over the first and second digit lines, respectively;

decoupling the first plate of the memory capacitor from the first digit line; and

decoupling the second plate of the memory capacitor from the second digit line.

16. The method of claim 15 wherein coupling the first plate of the memory capacitor to the first digit line and coupling the second plate of the memory capacitor to the second digit line comprises activating a first selection component and activating a second selection component, respectively.

17. The method of claim 15 wherein the coupling the first plate of the memory capacitor to the first digit line and the coupling the second plate of the memory capacitor to the second digit line are concurrent.

18. The method of claim 15 wherein amplifying the voltage difference to provide the amplified voltage difference comprises:

driving a first sense node of a sense component to ground and driving a second sense node of the sense component to a supply voltage responsive to the voltage of the second plate of the memory capacitor being greater than the reference voltage; and

driving the first sense node of a sense component to the supply voltage and driving a second sense node of the sense component to ground responsive to the voltage of the second plate of the memory capacitor being less than the reference voltage.

19. The method of claim 15 wherein the memory capacitor comprises a ferroelectric memory capacitor.

20. The method of claim 15, further comprising activating a sense component coupled to the second plate and provided the reference voltage.

21. A method, comprising:

driving a read voltage on a first digit line coupled to a first plate of a ferroelectric memory cell to cause a voltage change at a second plate of the ferroelectric memory cell, the voltage change at the second plate of the ferroelectric memory cell provided to a second sense node of a sense amplifier over a second digit line coupled to the second plate of the ferroelectric memory cell;

providing a reference voltage to a first sense node of the sense amplifier;

comparing the voltage at the second sense node of the sense amplifier to the voltage of the first sense node;

driving the first and second sense nodes to complementary voltage levels based on the comparison;

coupling the first sense node to the first digit line to provide the complementary voltage levels to the first and second plates of the ferroelectric memory cell over the first and second digit lines, respectively; and

isolating the first and second plates from the first and second digit lines, respectively.

22. The method of claim 21, further comprising:

driving the first and second sense nodes to opposite complementary voltage levels,

wherein the opposite complementary voltage levels are coupled to the first and second plates to change the polarization of the ferroelectric memory cell.

23. The method of claim 21, further comprising decoupling the second node from the second digit line prior to comparing the voltage at the second sense node of the sense amplifier to the voltage of the first sense node.

24. The method of claim 23, further comprising coupling the second node to the second digit line after driving the first and second sense nodes to complementary voltage levels based on the comparison.

25. The method of claim 21, wherein coupling the first sense node to the first digit line to provide the complementary voltage levels to the first and second plates of the ferroelectric memory cell over the first and second digit lines, respectively, and isolating the first and second plates from the first and second digit lines, respectively, restores data on the ferroelectric memory cell.

26. The method of claim 21, further comprising driving the first and second sense nodes to a same voltage prior to isolating the first and second plates from the first and second digit lines.

27. The method of claim 21 wherein the complementary voltage levels comprise a supply voltage and ground.