Memory systems and methods for improved power management

• US 10,074,417 B2
• Filed: 11/04/2015
• Issued: 09/11/2018
• Est. Priority Date: 11/20/2014
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Harris, James E.
• Primary Examiner(s): Tran, Michael
• Application Number:
  US15/522,182
• Publication Number:
  US 20170337965A1
• Time in Patent Office: 1,042 Days
• Field of Search: 36518905, 3652335
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

Claims

1. A variable-data-width memory module comprising:

a module interface to receive module commands, the module commands including encoded chip-select information;

a buffer system coupled to the module interface to receive the module commands, the buffer system including;

a configuration register to store a data-width-configuration value;

a chip-select decoder to decode the encoded chip-select information and the data-width-configuration value into memory-device clock-enable signals; and

a memory-device interface having clock-enable nodes, each clock-enable node to issue a respective one of the memory-device clock-enable signals; and

memory devices coupled to the memory-device interface, each memory device coupled to a respective one of the clock-enable nodes to receive the respective one of the memory-device clock-enable signals.

2. The variable-data-width memory module of claim 1, the buffer system further comprising a command decoder to decode memory-device chip-select signals from the encoded chip-select information, each memory device to receive a respective one of the memory-device chip-select signals.

3. The variable-data-width memory module of claim 1, wherein the module interface sends and receives data, the buffer system including:

a command-buffer component to interpret the module commands; and

at least one data-buffer component coupled between the module interface and the memory devices, the at least one data-buffer component to buffer the data between the module interface and the memory devices.

6. The memory module of claim 3, wherein the at least one data-buffer component issues the memory-device clock-enable signals.

4. A memory module comprising:

a module interface to receive module commands and send and receive data, the module commands including encoded chip-select information;

a buffer system coupled to the module interface to receive the module commands, the buffer system including;

a chip-select decoder to decode the encoded chip-select information into memory-device clock-enable signals;

a memory-device interface having clock-enable nodes, each clock-enable node to issue a respective one of the memory-device clock-enable signals;

a command-buffer component to interpret the module commands; and

at least one data-buffer component coupled between the module interface and the memory devices, the at least one data-buffer component to buffer the data between the module interface and the memory devices; and

memory devices coupled to the memory-device interface, each memory device coupled to a respective one of the clock-enable nodes to receive the respective clock-enable signal;

the at least one data-buffer component including multiple data-buffer components, each coupled to at least one of the memory devices and at least one other of the data-buffer components.

5. The memory module of claim 4, wherein the data-buffer components comprise data connections to convey data between the data-buffer components.

7. A memory module comprising:

a module interface to receive module commands, the module commands including encoded chip-select information;

a buffer system coupled to the module interface to receive the module commands, the buffer system including;

a chip-select decoder to decode the encoded chip-select information into memory-device clock-enable signals; and

a memory-device interface having clock-enable nodes, each clock-enable node to issue a respective one of the memory-device clock-enable signals;

memory devices coupled to the memory-device interface, each memory device coupled to a respective one of the clock-enable nodes to receive the respective clock-enable signal; and

a configuration register to store a configuration value, the chip-select decoder to decode the encoded chip-select information into the memory-device clock-enable signals based on the configuration value.

8. The memory module of claim 7, wherein the configuration value determines a number of the memory-device clock-enable signals to assert responsive to the encoded chip-select information.

9. A memory module comprising:

a module interface to receive module commands, the module commands including encoded address and chip-select information;

a buffer system coupled to the module interface to receive the module commands, the buffer system including;

a chip-select decoder to decode the chip-select information into memory power-state signals; and

a memory-device interface having power-state-signal nodes, each power-state-signal node to issue a respective one of the memory power-state signals; and

memory devices coupled to the memory-device interface and supporting an access mode and a low-power mode, each memory device coupled to a respective one of the power-state-signal nodes to receive the respective power-state signal, and to enter and exit the low-power mode responsive to the power-state signal.

10. The memory module of claim 9, wherein the buffer system decodes the chip-select information from one of the module commands to both derive the memory power-state signals for a memory transaction and to derive chip-select signals for a subset of the memory devices.

11. The memory module of claim 10, wherein the buffer system directs the power-state signals and the chip-select signals to the same subset of the memory devices.

12. The memory module of claim 9, wherein the buffer system applies a configuration value to the decoding of the chip-select information to determine a number of the power-state signals to issues responsive to the chip-select information.

13. The memory module of claim 12, further comprising a register to store the configuration value.

14. The memory module of claim 9, wherein the chip-select decoder decodes the chip-select information from a first command into the memory power-state signals and decodes the chip-select information from a second command into chip-select signals.

15. The memory module of claim 14, wherein the buffer system directs the chip-select signals and the power-state signals to the same subset of the memory devices.

16. The memory module of claim 9, wherein the buffer system includes a command-buffer component and data-buffer components, wherein the command-buffer component conveys the chip-select information to the data-buffer components and the data-buffer components decode the chip-select information into the power-state signals.

17. The memory module of claim 9, wherein the memory devices include chip-select input node coupled to respective ones of the power-state-signal nodes.