Device with decreased pitch contact to active regions

• US 10,074,571 B1
• Filed: 03/07/2017
• Issued: 09/11/2018
• Est. Priority Date: 03/07/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Greene, Brian J., Narasimha, Shreesh, Stiffler, Scott R.
• Primary Examiner(s): Valentine, Jami M
• Application Number:
  US15/451,869
• Publication Number:
  US 20180261512A1
• Time in Patent Office: 553 Days
• Field of Search: 438283
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A fin cut process cuts semiconductor fins after forming sacrificial gate structures that overlie portions of the fins. Selected gate structures are removed to form openings and exposed portions of the fins within the openings are etched. An isolation dielectric layer is deposited into the openings and between end portions of the cut fins. The process enables a single sacrificial gate structure to define the spacing between two active regions on dissimilar electrical nets.

Claims

1. A method of forming a semiconductor device, comprising:

fabricating a plurality of parallel fins on a semiconductor substrate;

forming a plurality of sacrificial gate structures overlying a channel portion of each of the fins;

forming sidewall spacers on sidewalls of the sacrificial gate structures, the sidewall spacers abutting top and sidewall surfaces of the fins;

forming a first dielectric layer over the fins and over the sidewall spacers, the first dielectric layer disposed between adjacent sacrificial gate structures;

removing a first sacrificial gate structure from over the channel portion of at least one fin to form an opening exposing the channel portion;

removing the channel portion of the at least one fin exposed through the opening to form a cut fin; and

forming an isolation dielectric layer within the opening and between opposing end surfaces of the cut fin.

2. The method of claim 1, wherein the sacrificial gate structures have a width of 10 to 30 nm.

3. The method of claim 1, further comprising forming source and drain junctions over exposed portions of the fins prior to forming the first dielectric layer over the fins.

4. The method of claim 1, wherein the first sacrificial gate structure is removed selective to the sidewall spacers.

5. The method of claim 4, wherein an end surface of the cut fin is co-planar with a surface of one of the sidewalls spacers.

6. The method of claim 4, wherein each end surface of the cut fin is co-planar with a respective surface of the sidewalls spacers.

7. The method of claim 1, wherein a distance between opposing end surfaces of the cut fin is 10 to 30 nm.

8. The method of claim 1, wherein the sidewall spacers comprise silicon nitride and the first dielectric layer comprises silicon dioxide.

9. The method of claim 1, wherein the isolation dielectric layer comprises a dielectric material selected from the group consisting of an oxide, a nitride and an oxynitride.

10. The method of claim 1, wherein a top surface of the isolation dielectric layer is co-planar with a top surface of an adjacent sacrificial gate structure.

11. The method of claim 1, further comprising:

removing a second sacrificial gate structure from over the channel portion of the at least one fin to form a cavity exposing the channel portion; and

forming a gate stack conformally over exposed portions of the fin within the cavity.

12. The method of claim 1, further comprising:

removing the first dielectric layer to form contact openings; and

forming a conductive contact structure within the contact openings.

13. The method of claim 1, wherein removing the channel portion completely severs the at least one fin to form a first fin segment and a second fin segment.

14. The method of claim 13, wherein the isolation dielectric electrically isolates the first fins segment from the second fin segment.

15. A method of forming a semiconductor device, comprising:

forming a plurality of sacrificial gate structures overlying channel portions of a semiconductor fin;

forming sidewall spacers on sidewalls of the sacrificial gate structures, the sidewall spacers abutting top and sidewall surfaces of the fin;

removing a first sacrificial gate structure from over the channel portion to form an opening exposing the channel portion; and

removing the channel portion of the fin exposed through the opening to form a cut fin.

16. The method of claim 15, wherein an end surface of the cut fin is co-planar with a surface of one of the sidewalls spacers.

17. The method of claim 15, wherein each end surface of the cut fin is co-planar with a respective sidewall spacer exposed surface.

18. The method of claim 15, further comprising forming an isolation dielectric layer within the opening and between opposing end surfaces of the cut fin.

19. The method of claim 15, further comprising:

removing a second sacrificial gate structure from over the channel portion of the fin to form a cavity exposing the channel portion; and

forming a gate stack conformally over exposed portions of the fin within the cavity.