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Memory cell and array structure having a plurality of bit lines

  • US 10,074,605 B2
  • Filed: 11/16/2016
  • Issued: 09/11/2018
  • Est. Priority Date: 06/30/2016
  • Status: Active Grant
First Claim
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1. A memory device comprising:

  • an array of memory cells;

    a first bit-line coupled to memory cells of a first column of the array of memory cells, wherein the first bit-line is disposed on a first metal layer;

    a second bit-line coupled to the first bit-line, wherein the second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via, wherein the at least one via is disposed on a first edge cell region of the array and wherein another via coupling the first and second bit-lines is disposed on a second edge cell region of the array, the second edge cell region on an opposing side of the array from the first edge cell region; and

    a word line coupled to a row of the array of memory cells.

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