Memory cell and array structure having a plurality of bit lines

• US 10,074,605 B2
• Filed: 11/16/2016
• Issued: 09/11/2018
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Jhon Jhy
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US15/353,618
• Publication Number:
  US 20180005938A1
• Time in Patent Office: 664 Days
• Field of Search: 257758
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/18 Peripheral circuit regions
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 20/27 ROM only
• CPC Class Codes: H10B 20/65 of memory structures of the ROM only type

Abstract

Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The first bit-line is disposed on a first metal layer. A second bit-line is coupled to the first bit-line. The second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via. A word line is coupled to a row of the array of memory cells.

Claims

1. A memory device comprising:

an array of memory cells;

a first bit-line coupled to memory cells of a first column of the array of memory cells, wherein the first bit-line is disposed on a first metal layer;

a second bit-line coupled to the first bit-line, wherein the second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via, wherein the at least one via is disposed on a first edge cell region of the array and wherein another via coupling the first and second bit-lines is disposed on a second edge cell region of the array, the second edge cell region on an opposing side of the array from the first edge cell region; and

a word line coupled to a row of the array of memory cells.

2. The memory device of claim 1, further comprising:

a first complement bit-line coupled to memory cells of the first column of the array of memory cells, wherein the first complement bit-line is disposed on the first metal layer; and

a second complement bit-line coupled to the first complement bit-line, wherein the second complement bit-line is coupled to the first complement bit-line at at least two locations, wherein the second complement bit-line is disposed on the second metal layer.

3. The memory device of claim 1, further comprising:

a second word line coupled to the word line and associated the row of the array.

4. The memory device of claim 1, wherein the second metal layer is above the first metal layer, and wherein the word line is on a third metal layer above the second metal layer, wherein the second metal layer is a next adjacent metal layer to the first metal layer.

5. The memory device of claim 1, wherein the first metal layer and the second metal layer are part of a multi-layer interconnect (MLI), the first metal layer being Metal 1 (M1) and the second metal layer being Metal 3 (M3) layer, and wherein the word line is part of the MLI and is disposed on Metal 2 (M2), M2 being above M1 and M3 being above M2.

6. The memory device of claim 1, wherein the first bit-line is connected to a transistor of a memory cell of the first column of the array of memory cells through a second via extending below the first metal layer.

7. The memory device of claim 1, wherein the row and column are in a first array of memory cells, and wherein the memory device further comprises:

a second array of memory cells spaced from the first array of memory cells;

a third bit-line coupled to memory cells of a first column of the second array of memory cells, wherein the third bit-line is disposed on the first metal layer;

a fourth bit-line coupled to the third bit-line, wherein the fourth bit-line is coupled to the third bit-line, wherein the fourth bit-line is disposed on the second metal layer; and

another word line coupled to a row of the second array of memory cells.

8. The memory device of claim 1, wherein the array of memory cells are one of DRAM, SRAM, ROM.

12. The memory device of claim 1, wherein the first bit-line is disposed between the second bit-line and a top surface of a substrate, the array of memory cells disposed on the substrate.

13. The memory device of claim 1, wherein the at least one via physically interfaces the first bit-line on the first metal layer.

14. The memory device of claim 13, wherein the at least one via physically interfaces the second bit-line on the second metal layer.

9. A memory device comprising:

an array of memory cells;

a first bit-line coupled to memory cells of a first column of the array of memory cells, wherein the first bit-line is disposed on a first metal layer;

a second bit-line coupled to the memory cells of the first column of the array of memory cells, wherein the second bit-line is disposed on a second metal layer above the first metal layer and the second bit-line is coupled to the first bit-line by a first via extending from an interface with the first bit-line on the first metal layer to an interface with the second bit-line on the second metal layer;

a first complement bit-line coupled to memory cells of the first column of the array of memory cells, wherein the first complement bit-line is disposed on the first metal layer;

a second complement bit-line coupled to the first complement bit-line, wherein the second complement bit-line is disposed on the second metal layer; and

a word line coupled to a row of the array of memory cells.

10. The memory device of claim 9, wherein the first metal layer is Metal-1 (M1) of a multi-layer interconnect and the second metal layer is Metal-2 (M2) of the multi-layer interconnect.

11. The memory device of claim 10, wherein the word line is on Metal-3 (M3) of the multi-layer interconnect.

15. The memory device of claim 9, wherein a second via extends from an interface with the first complement bit-line on the first metal layer to an interface with the second complement bit-line on the second metal layer.

16. A memory device comprising:

an array of memory cells;

a first bit-line coupled a memory cell of a first column of the array of memory cells, the first bit-line on a first metal layer;

a via extending in a vertical direction from the first bit-line to a second metal layer above the first bit-line;

a second bit-line coupled to memory cells of the first column of the array of memory cells, wherein the second bit-line is disposed above the first bit-line, and wherein in the vertical direction, the via is between the second bit-line and the first bit-line, the via coupling the second bit-line to the first bit-line; and

a word line coupled to a row of the array of memory cells.

17. The memory device of claim 16, further comprising:

a first complement bit-line coupled to the first column of the array of memory cells.

18. The memory device of claim 17, wherein the memory device is a single port static random access memory (SRAM) device.

19. The memory device of claim 17, further comprising:

a second complement bit-line coupled to the first complement bit-line, wherein the second complement bit-line is disposed on the second metal layer and the first complement bit-line is disposed on the first metal layer.

20. The memory device of claim 17, wherein the second bit-line is on the second metal layer, and wherein the via extends from a physical interface with the first bit-line to a physical interface with the second bit-line.