Memory cell and array structure having a plurality of bit lines
First Claim
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1. A memory device comprising:
- an array of memory cells;
a first bit-line coupled to memory cells of a first column of the array of memory cells, wherein the first bit-line is disposed on a first metal layer;
a second bit-line coupled to the first bit-line, wherein the second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via, wherein the at least one via is disposed on a first edge cell region of the array and wherein another via coupling the first and second bit-lines is disposed on a second edge cell region of the array, the second edge cell region on an opposing side of the array from the first edge cell region; and
a word line coupled to a row of the array of memory cells.
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Abstract
Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The first bit-line is disposed on a first metal layer. A second bit-line is coupled to the first bit-line. The second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via. A word line is coupled to a row of the array of memory cells.
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Citations
20 Claims
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1. A memory device comprising:
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an array of memory cells; a first bit-line coupled to memory cells of a first column of the array of memory cells, wherein the first bit-line is disposed on a first metal layer; a second bit-line coupled to the first bit-line, wherein the second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via, wherein the at least one via is disposed on a first edge cell region of the array and wherein another via coupling the first and second bit-lines is disposed on a second edge cell region of the array, the second edge cell region on an opposing side of the array from the first edge cell region; and a word line coupled to a row of the array of memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 12, 13, 14)
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9. A memory device comprising:
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an array of memory cells; a first bit-line coupled to memory cells of a first column of the array of memory cells, wherein the first bit-line is disposed on a first metal layer; a second bit-line coupled to the memory cells of the first column of the array of memory cells, wherein the second bit-line is disposed on a second metal layer above the first metal layer and the second bit-line is coupled to the first bit-line by a first via extending from an interface with the first bit-line on the first metal layer to an interface with the second bit-line on the second metal layer; a first complement bit-line coupled to memory cells of the first column of the array of memory cells, wherein the first complement bit-line is disposed on the first metal layer; a second complement bit-line coupled to the first complement bit-line, wherein the second complement bit-line is disposed on the second metal layer; and a word line coupled to a row of the array of memory cells. - View Dependent Claims (10, 11, 15)
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16. A memory device comprising:
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an array of memory cells; a first bit-line coupled a memory cell of a first column of the array of memory cells, the first bit-line on a first metal layer; a via extending in a vertical direction from the first bit-line to a second metal layer above the first bit-line; a second bit-line coupled to memory cells of the first column of the array of memory cells, wherein the second bit-line is disposed above the first bit-line, and wherein in the vertical direction, the via is between the second bit-line and the first bit-line, the via coupling the second bit-line to the first bit-line; and a word line coupled to a row of the array of memory cells. - View Dependent Claims (17, 18, 19, 20)
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Specification