Bond pads with differently sized openings

• US 10,074,624 B2
• Filed: 08/07/2015
• Issued: 09/11/2018
• Est. Priority Date: 08/07/2015
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Venkatadri, Vikram
• Primary Examiner(s): Luu, Chuong A
• Application Number:
  US14/821,228
• Publication Number:
  US 20170040275A1
• Time in Patent Office: 1,131 Days
• Field of Search: 257773
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06153 with a staggered arrangement, e.g. depopulated array
• CPC Class Codes: H01L 2224/06155 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/0616 Random array, i.e. array with no symmetry
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

Integrated circuit dies are provide with a passivation layer having a plurality of differently sized openings exposing bond pads for bonding. The sizes of the bond pads vary in a manner that at least partially compensates for stresses during bonding, such as flip chip thermocompression bonding, due to asymmetric distribution of bond pads.

Claims

1. An integrated circuit die comprising:

a plurality of bond pads; and

a die passivation layer comprising polymer and having a plurality of differently sized openings exposing a plurality of the bond pads, positions of the differently sized openings distributed asymmetrically relative to an entire upper surface of the integrated circuit die in a top down view, wherein sizes of the differently sized openings are measured horizontally at an upper surface of the die passivation layer.

2. The integrated circuit die of claim 1, wherein the plurality of differently sized openings comprises two or more groups of openings, each group having a different average opening size relative to the other group(s).

3. The integrated circuit die of claim 2, wherein a size difference between average maximum lateral dimensions for two of the groups is greater than about 2 μ

m.

4. The integrated circuit die of claim 2, wherein the groups of openings correspond to two areal zones of the upper surface of the integrated circuit die in the top down view, including a first zone comprising a first half of the die and a second zone comprising a second half of the die, wherein the first and second zones have different average opening sizes.

5. The integrated circuit die of claim 4, wherein the openings of the first zone have a first average opening size and the openings of the second zone have a second average opening size, wherein the first average opening size is smaller than the second average opening size, and wherein the first zone has a higher number of exposed bond pads compared to the second zone.

6. The integrated circuit die of claim 5, the upper surface of the integrated circuit die having a first side, a second side opposite the first side, a third side, and a fourth side opposite the third side, wherein the first zone includes the third side and the second zone includes the fourth side, wherein the third side has a higher number of exposed bond pads compared to the fourth side.

7. The integrated circuit die of claim 1, wherein sizes of the plurality of the differently sized openings vary in a manner to at least partially compensate for stresses on the die due to the asymmetric distribution of the plurality of differently sized openings.

8. The integrated circuit die of claim 1, wherein the upper surface of the integrated circuit die has a first side, a second side opposite the first side, a third side, and a fourth side opposite the third side,

wherein the plurality of openings comprises differently sized openings along the first and second sides, a plurality of openings along the third side, and no openings along the fourth side.

9. The integrated circuit die of claim 8, wherein the openings on the first and second sides comprise at least three different sizes with the openings of the three different sizes having a smallest size positioned adjacent the third side and the openings of the three different sizes having a largest size positioned adjacent the fourth side.

10. The integrated circuit die of claim 1, wherein the openings comprise square openings in the top down view.

11. A packaged chip comprising:

a semiconductor die; and

a packaging substrate electrically connected to the die,

wherein the die includes a die passivation layer at an upper surface of the die, the die passivation layer having a plurality of differently sized openings exposing a corresponding plurality of bond pads and the die is electrically connected to the packaging substrate through the differently sized openings, wherein sizes of the differently sized openings are measured horizontally at an upper surface of the die passivation layer.

12. The packaged chip of claim 11, the semiconductor die further comprising a plurality of asymmetrically distributed bond pads, wherein the plurality of differently sized openings expose a corresponding plurality of the bond pads.

13. The packaged chip of claim 11, wherein the plurality of different sized openings comprises two or more groups of openings, each group having a different average opening size.

14. The packaged chip of claim 13, wherein the groups of openings correspond to two zones of the die, including a first zone comprising a first half of the die and a second zone comprising a second half of the die, wherein the first zone has a different average opening size compared to the second zone.

22. The packaged chip of claim 11, wherein the packaging substrate is electrically connected to the die via thermocompression bonding, and wherein the plurality of differently sized openings is configured to reduce stress gradients in the die from the thermocompression bonding relative to openings having a uniform size.

15. A method of packaging an integrated circuit die, the method comprising:

providing a die having a plurality of bond pads;

forming a passivation layer comprising polymer on the die; and

creating a plurality of differently sized openings in the passivation layer to expose a corresponding plurality of the bond pads, positions of the differently sized openings distributed asymmetrically relative to an entire upper surface of the integrated circuit die in a top down view, wherein sizes of the differently sized openings are measured horizontally at an upper surface of the die passivation layer.

16. The method of claim 15, wherein the passivation layer comprises polyimide.

17. The method of claim 15, wherein the passivation layer further comprises an inorganic dielectric layer.

18. The method of claim 15, wherein the plurality of differently sized openings comprises a plurality of groups of openings, each group having a different average opening size.

19. The method of claim 18, further comprising positioning the plurality of differently sized openings such that a first group has a first average opening size and is positioned in a first zone of the upper surface of the integrated circuit die in a top down view having a first areal density of bond pads, and a second group having a second average opening size and is positioned in a second zone of the upper surface of the integrated circuit die in a top down view having a second areal density of bond pads, wherein the first average opening size is smaller than the second average opening size, and the first areal density of bond pads is greater than the second areal density of bond pads.

20. The method of claim 15, further comprising flip chip attaching the die to a packaging substrate.

21. The method of claim 15, further comprising varying sizes of the plurality of the differently sized openings in a manner to at least partially compensate for stresses on the die due to the asymmetric distribution of the plurality of differently sized openings.

23. The method of claim 15, further comprising thermocompression bonding the die to a packaging substrate through the differently sized openings.

24. The method of claim 15, further comprising positioning the plurality of differently sized openings to reduce stress gradients in the die relative to uniform opening sizes.