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Asymmetric semiconductor memory device having electrically floating body transistor

  • US 10,074,653 B2
  • Filed: 11/19/2016
  • Issued: 09/11/2018
  • Est. Priority Date: 03/24/2011
  • Status: Active Grant
First Claim
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1. An asymmetric bi-stable semiconductor memory cell comprising:

  • a first bipolar device having a first floating base region, a first emitter, and a first collector; and

    a second bipolar device having a second floating base region, a second emitter, and a second collector,wherein said first floating base region and said second floating base region comprise a common floating base region and wherein said common floating base region comprises means for storing a charge or lack of charge as a volatile memory indicative of a state of the asymmetric semiconductor memory cell;

    wherein said first collector is common to said second collector;

    wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell, andwherein performance characteristics of said first bipolar device are different from performance characteristics of said second bipolar device.

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