Asymmetric semiconductor memory device having electrically floating body transistor

• US 10,074,653 B2
• Filed: 11/19/2016
• Issued: 09/11/2018
• Est. Priority Date: 03/24/2011
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): NGUYEN, DUY T V
• Application Number:
  US15/356,540
• Publication Number:
  US 20170092648A1
• Time in Patent Office: 661 Days
• Field of Search: 257204, 257205
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/7308 Schottky transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.

Claims

1. An asymmetric bi-stable semiconductor memory cell comprising:

a first bipolar device having a first floating base region, a first emitter, and a first collector; and

a second bipolar device having a second floating base region, a second emitter, and a second collector,

wherein said first floating base region and said second floating base region comprise a common floating base region and wherein said common floating base region comprises means for storing a charge or lack of charge as a volatile memory indicative of a state of the asymmetric semiconductor memory cell;

wherein said first collector is common to said second collector;

wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell, and

wherein performance characteristics of said first bipolar device are different from performance characteristics of said second bipolar device.

2. The asymmetric bi-stable semiconductor memory cell of claim 1, further comprising a gate positioned above said common floating base region.

3. The asymmetric bi-stable semiconductor memory cell of claim 2, further comprising:

a substrate; and

a buried layer buried in said substrate;

wherein said buried layer comprises said first and second collectors; and

wherein said substrate is separated from said common floating base region by said buried layer.

4. The asymmetric semiconductor memory cell of claim 3, further comprising:

a word line terminal electrically connected to said gate;

a bit line terminal electrically connected to said first emitter;

a source line terminal electrically connected to said second emitter;

a buried well terminal electrically connected to said buried layer; and

a substrate terminal electrically connected to said substrate.

5. The asymmetric bi-stable semiconductor memory cell of claim 2, further comprising a gap region on a surface of said common floating base region, said gap region located between one of said first bipolar device or second bipolar device and said gate.

6. The asymmetric semiconductor memory cell of claim 2, further comprising an insulating layer insulating said gate from said common floating base region.

7. The asymmetric bi-stable semiconductor memory cell of claim 1, wherein

said common floating base region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

said first collector and said second collector have a second conductivity type selected from said p-type conductivity type and said n-type conductivity type, said second conductivity type being different from said first conductivity type; and

a second region having said second conductivity type, said second region being separated from at least one of said first and second collectors by said common floating base region.

8. The asymmetric bi-stable semiconductor memory cell of claim 1, arranged in an array of said asymmetric bi-stable semiconductor memory cells comprising at least one row of said cells and a plurality of columns of said cells or at least one column of said cells and a plurality of rows of said cells.

9. The asymmetric bi-stable semiconductor memory cell of claim 1, wherein one of said first emitter or second emitter comprises an electrode electrically connected to said first floating base region and second floating base region, wherein said electrode forms a Schottky contact with said first floating base region and second floating base region.

10. The asymmetric bi-stable semiconductor memory cell of claim 1, wherein at least said first floating base region, said first emitter, said second floating base region and said second emitter are formed in a fin structure.

11. A semiconductor memory array comprising:

a plurality of asymmetric bi-stable semiconductor memory cells arranged in a matrix of rows and columns, wherein each said asymmetric bi-stable semiconductor memory cell includes;

a first bipolar device having a first floating base region, a first emitter, and a first collector; and

a second bipolar device having a second floating base region, a second emitter, and a second collector,

wherein a common floating base region comprises said first floating base region and said second floating base region and wherein said common floating base region comprises means for storing a charge or lack of charge as a volatile memory indicative of a state of the asymmetric semiconductor memory cell;

wherein said first collector is common to said second collector;

wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell,

wherein performance characteristics of said first bipolar device are different from performance characteristics of said second bipolar device; and

wherein said first and second collectors are commonly connected to at least two of said memory cells.

12. The semiconductor memory array of claim 11, wherein each said asymmetric bi-stable semiconductor memory cell further comprises a gate positioned above said common floating base region.

13. The semiconductor memory array of claim 12, wherein each said asymmetric bi-stable semiconductor memory cell further comprises a gap region on a surface of said common floating base region, said gap region located between one of said first bipolar device or second bipolar device and said gate.

14. The semiconductor memory array of claim 11, further comprising:

a substrate; and

a buried layer buried in said substrate;

wherein said buried layer includes said first and second collectors; and

wherein said substrate is separated from said common floating base region by said buried layer.

15. The semiconductor memory array of claim 14, further comprising:

a word line terminal electrically connected to said gates of a plurality of said asymmetric bi-stable semiconductor memory cells in a row;

a bit line terminal electrically connected to said first emitters of a second plurality of said asymmetric bi-stable semiconductor memory cells in a column;

a source line terminal electrically connected to said second emitters of said plurality of asymmetric bi-stable semiconductor memory cells in a row;

a buried well terminal electrically connected to said buried layer of a third plurality of asymmetric bi-stable semiconductor memory cells; and

a substrate terminal electrically connected to said substrate of a fourth plurality of asymmetric bi-stable semiconductor memory cells.

16. The semiconductor memory array of claim 12, wherein each said asymmetric bi-stable memory cell further comprises an insulating layer insulating said gate from said common floating base region.

17. The semiconductor memory array of claim 11, wherein

said common floating base region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

said first collector and said second collector have a second conductivity type selected from said p-type conductivity type and said n-type conductivity type, said second conductivity type being different from said first conductivity type; and

a second region having said second conductivity type, said second region being separated from at least one of said first and second collectors by said common floating base region.

18. The semiconductor memory array of claim 11, wherein one of said first emitter or second emitter comprises an electrode electrically connected to said first floating base region and second floating base region, wherein said electrode forms a Schottky contact with said first floating base region and second floating base region.

19. The semiconductor memory array of claim 11, wherein at least said first floating base region, said first emitter, said second floating base region and said second emitter are formed in a fin structure.