Semiconductor memory device

• US 10,074,667 B1
• Filed: 08/28/2017
• Issued: 09/11/2018
• Est. Priority Date: 03/10/2017
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Higashi, Kazuyuki, Tsumura, Kazumichi, Katsumata, Ryota, Arai, Fumitaka
• Primary Examiner(s): Tran, Minh-Loan
• Application Number:
  US15/688,561
• Publication Number:
  US 20180261623A1
• Time in Patent Office: 379 Days
• Field of Search: None
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/23 with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/00 EEPROM devices comprising charge-trapping gate insulators
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 : characterised by the boundary region between the core and peripheral circuit regions

Abstract

A semiconductor memory device includes a first memory cell array layer includes a first memory cell array region, in which memory cells are 3-dimensionally arrayed, and a first and second surface wiring layer connected to the memory cells. A second memory cell array layer includes second memory cell array region, in which memory cells are 3-dimensionally arrayed, and a third and fourth surface wiring layer connected to the second plurality of memory cells. The first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other. The first and second memory cell array regions overlap each other as viewed from a direction orthogonal to a layer plane.

Claims

1. A semiconductor memory device, comprising:

a first memory cell array layer having a first surface, a second surface opposite to the first surface, a first memory cell array region in which a first plurality of memory cells is 3-dimensionally arrayed, and a first surface wiring layer and a second surface wiring layer at the first surface and the second surface, respectively, and connected to the first plurality of memory cells; and

a second memory cell array layer having a third surface, a fourth surface opposite the third surface, a second memory cell array region in which a second plurality of memory cells is 3-dimensionally arrayed, and a third surface wiring layer and the fourth surface wiring layer at the third surface and the fourth surface, respectively, and connected to the second plurality of memory cells, wherein

the first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other, and the first and second memory cell array regions overlap each other as viewed from a direction orthogonal to the first surface.

2. The semiconductor memory device according to claim 1, further comprising:

a peripheral circuit layer bonded to the first surface of the first memory cell array layer and electrically connected to the first plurality of memory cells.

3. The semiconductor memory device according to claim 2, wherein the peripheral circuit layer includes a silicon substrate layer.

4. The semiconductor memory device according to claim 1, further comprising:

a third memory cell array layer having a fifth surface, a sixth surface opposite the fifth surface, a third memory cell array region in which a third plurality of memory cells are 3-dimensionally arrayed, a fifth surface wiring layer at the fifth surface and connected to the third plurality of memory cells, wherein

the third memory cell array layer is bonded to second memory cell array layer such that the fifth surface wiring layer is bonded to a fourth surface wiring layer at the fourth surface of the second memory cell array layer.

5. The semiconductor memory device according to claim 1, wherein the second and third surface wiring layers are disposed outside the first and second memory cell array regions as viewed from the direction orthogonal to the first surface.

6. The semiconductor memory device according to claim 1, wherein at least a portion of the second surface wiring layer and a portion of the third surface wiring layer are disposed inside the first and second memory cell array regions as viewed from the direction orthogonal to the first surface.

7. The semiconductor memory device according to claim 1, wherein in at least one of the first and second memory cell array layers includes a memory string that includes a memory cell storing an array layer ID and a transistor for selecting memory cell array layers according to the array layer ID.

8. A semiconductor memory device, comprising:

a peripheral circuit layer that includes a circuit substrate, a control circuit formed on a circuit formation surface of the circuit substrate, and a circuit-side wiring layer formed at the circuit formation surface and electrically connected to the control circuit;

a first memory cell array layer having a first surface, a second surface opposite to the first surface, a first memory cell array region in which a first plurality of memory cells is 3-dimensionally arrayed, a first signal line extraction electrode electrically connected to the first plurality of memory cells, a first external connection electrode disposed outside the first memory cell array region, as viewed in a direction orthogonal to the first surface, and electrically connected to the control circuit, a first surface wiring layer at the first surface and connected to the first signal line extraction electrode, and a second surface wiring layer at the second surface and connected to the first external connection electrode; and

a second memory cell array layer having a third surface, a fourth surface opposite to the third surface, a second memory cell array region in which a second plurality of memory cells is 3-dimensionally arrayed, a second signal line extraction electrode electrically connected to the second plurality of memory cells, a second external connection electrode disposed outside the second memory cell array region, as viewed in the direction orthogonal to the first surface, and electrically connected to the first external connection electrode, a third surface wiring layer at the third surface and connected to the second signal line extraction electrode, and a fourth surface wiring layer at the fourth surface and connected to the second external connection electrode, wherein,

the first surface faces the peripheral circuit layer,

the circuit-side wiring layer and the first surface wiring layer are bonded to each other,

the third surface faces the first memory cell array layer, and

the second surface wiring layer and the third surface wiring layer are bonded to each other.

9. The semiconductor memory device according to claim 8, wherein neither of the first or second memory cell array layers include a substrate.

10. The semiconductor memory device according to claim 8, wherein

the circuit-side wiring layer and the first surface wiring layer are directly bonded to each other, and

the second surface wiring layer and the third surface wiring layer are directly bonded to each other.

11. The semiconductor memory device according to claim 8, wherein the first plurality of memory cells comprises:

a first stacked body in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked,

first columnar portions extending in a stacking direction in the first stacked body,

a first bit line electrically connected to the first columnar portions on a side of the first surface,

a first source line electrically connected to the first columnar portions on a side of the second surface, and

a first source-side wiring layer disposed closer to the second surface than the first source line.

12. The semiconductor memory device according to claim 11, wherein the second plurality of memory cells comprises:

a second stacked body in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked,

second columnar portions extending in a stacking direction in the second stacked body,

a second bit line electrically connected to the second columnar portions on a side of the third surface,

a second source line electrically connected to the second columnar portions on a side of the fourth surface, and a second source-side wiring layer disposed closer to the fourth surface than the second source line.

13. The semiconductor memory device according to claim 12, wherein

the first source-side wiring layer is connected to the second bit line at a position inside the first and second memory cell array regions when viewed in the direction orthogonal to the first surface.

14. The semiconductor memory device according to claim 8, wherein the second plurality of memory cells comprises:

a stacked body in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked,

columnar portions extending in a stacking direction in the stacked body,

a bit line electrically connected to the columnar portions on a side of the third surface,

a source line electrically connected to the columnar portions on a side of the fourth surface, and a source-side wiring layer disposed closer to the fourth surface than the second source line.

15. The semiconductor memory device according to claim 8, wherein

the second surface wiring layer is connected to the first signal line extraction electrode at a position inside the first memory cell array region, when viewed in the direction orthogonal to the first surface, and

the third surface wiring layer is connected to the second signal line extraction electrode at a position inside the second memory cell array region, when viewed in the direction orthogonal to the first surface.

16. The semiconductor memory device according to claim 8, further comprising:

a third memory cell array layer stacked on the second memory cell array layer.

17. The semiconductor memory device according to claim 8, further comprising:

a memory string in the first memory cell array layer, the memory string including a memory cell storing an array layer ID and a transistor for selecting the first memory cell array layer, the memory string being electrically connected to the first signal line extraction electrode.

18. The semiconductor memory device according to claim 8, wherein at least one of the first and second memory cell array layers includes a memory string that includes a memory cell storing an array layer ID and a transistor for selecting memory cell array layers according to the array layer ID.

19. The semiconductor memory device according to claim 8, further comprising:

an array layer select circuit configured to select a memory cell array layer according to an array layer ID, wherein

wherein a part of the array layer select circuit is formed for each memory block of the first memory cell array layer.

20. The semiconductor memory device according to claim 8, wherein the circuit substrate is a silicon substrate.