Method of manufacturing semiconductor unit and the semiconductor unit

• US 10,074,686 B2
• Filed: 09/11/2017
• Issued: 09/11/2018
• Est. Priority Date: 09/10/2015
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kimura, Masatoshi
• Primary Examiner(s): Menz, Laura
• Application Number:
  US15/700,364
• Publication Number:
  US 20170373112A1
• Time in Patent Office: 365 Days
• CPC Class Codes: H01L 27/14607 Geometry of the photosensitive area
• CPC Class Codes: H01L 27/1461 characterised by the photosensitive area
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

In a solid-state imaging device including a plurality of pixels each pixel including a plurality of photodiodes, it is prevented that an incidence angle of incident light on the solid-state imaging device becomes large in a pixel in an end of the solid-state imaging device, causing a difference in output between the two photodiodes in the pixel, and thus autofocus detection accuracy is deteriorated. Photodiodes extending in a longitudinal direction of a pixel allay section are provided in each pixel. The photodiodes in the pixel are arranged in a direction orthogonal to the longitudinal direction of the pixel allay section.

Claims

1. A method of manufacturing a semiconductor unit comprising a solid-state imaging device including a plurality of pixels in a pixel array section, each pixel including a first photodiode and a second photodiode, the method comprising:

(a) providing a semiconductor substrate;

(b) forming a well region having a first conductivity type in a main surface of the semiconductor substrate;

(c) after (b), forming a first semiconductor region having the first conductivity type in the main surface of the semiconductor substrate, the first semiconductor region extending in a first direction along the main surface of the semiconductor substrate; and

(d) forming a second semiconductor region having a second conductivity type different from the first conductivity type in a top of the well region, the second semiconductor region overlapping with the first semiconductor region in plan view,

wherein the second semiconductor region is divided by the first semiconductor region into a first portion that configures the first photodiode and a second portion that configures the second photodiode, and

wherein a first pixel among the plurality of pixels is located closer to a first end of the pixel array section in a second direction orthogonal to the first direction than an opposite second end of the pixel array section in the second direction, and

a width in the second direction of the first photodiode of the first pixel is smaller than a width in the second direction of the second photodiode the first pixel.

2. The method according to claim 1, further comprising:

(b1) after (b) and before (c), forming an element isolating region surrounding an active region,

wherein in each of the pixels, the first photodiode and the second photodiode are provided in the active region, and

wherein a shortest distance in the second direction between the first photodiode, which is formed closer to the first end than the second photodiode, and the element isolating region of the first pixel is smaller than a shortest distance in the second direction between the first photodiode, which is formed closer to the first end than the second photodiode, and the element isolating region of a second pixel among the plurality of pixels,

wherein the second pixel is closer to a center of the pixel array section in the second direction than the first pixel.

3. The method according to claim 2, further comprising:

(b2) after (b), forming, in contact with the element isolating region, a third semiconductor region having the first conductivity type and having an impurity concentration higher than an impurity concentration of the well region in a surface of the semiconductor substrate,

wherein in the first pixel, a part of a region forming the third semiconductor region overlaps with a part of a region forming the second semiconductor region on a side closer to the first end than the second end in plan view.

4. The method according to claim 2,

wherein, in (d), the formed second semiconductor region comprises a pair of semiconductor regions spaced apart from each other in the second direction, and

wherein one of the pair of semiconductor regions is in contact with one end of the first semiconductor region, and

wherein the other of the pair of semiconductor regions is in contact with another end of the first semiconductor region.

5. The method according to claim 4,

wherein a first region of one of the pair of semiconductor regions overlaps with a region forming the first semiconductor region and is closer to the first end than the second end,

wherein a second region of the other of the pair of semiconductor regions overlaps with the region forming the first semiconductor region, and

wherein a width in the second direction of the first region is larger than a width in the second direction of the second region.

6. The method according to claim 4, wherein the pixel array section extends in the second direction.