Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack
First Claim
1. An integrated circuit structure, comprising:
- a nanowire above a substrate, the nanowire comprising a group III-V material;
a gate stack on and completely surrounding a channel region of the nanowire, the gate stack comprising;
a first dielectric layer on outer portions, but not an inner portion, of the channel region;
a second, different, dielectric layer conformal with the first dielectric layer and on the inner portion of the channel region; and
a gate electrode on the second dielectric layer;
a bottom barrier layer between the substrate and the nanowire, wherein a bottom portion of the gate stack is on the bottom barrier layer; and
source and drain regions on either side of the gate stack.
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Abstract
Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
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Citations
20 Claims
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1. An integrated circuit structure, comprising:
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a nanowire above a substrate, the nanowire comprising a group III-V material; a gate stack on and completely surrounding a channel region of the nanowire, the gate stack comprising; a first dielectric layer on outer portions, but not an inner portion, of the channel region; a second, different, dielectric layer conformal with the first dielectric layer and on the inner portion of the channel region; and
a gate electrode on the second dielectric layer;a bottom barrier layer between the substrate and the nanowire, wherein a bottom portion of the gate stack is on the bottom barrier layer; and source and drain regions on either side of the gate stack. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit structure, comprising:
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a nanowire above a substrate, the nanowire comprising a group III-V material; a gate stack on and completely surrounding a channel region of the nanowire, the gate stack comprising; a first dielectric layer on the channel region; a second, different, dielectric layer conformal with the first dielectric layer and on the first dielectric layer, but not on the channel region; and a gate electrode on the second dielectric layer; and
source and drain regions on either side of the gate stack. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification