Trench MOSFET shield poly contact

• US 10,074,743 B2
• Filed: 05/25/2017
• Issued: 09/11/2018
• Est. Priority Date: 03/27/2015
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Qin, Ganming, De Fresart, Edouard D., Ku, Pon Sung, Petras, Michael F., Zitouni, Moaniss, Zupac, Dragan
• Primary Examiner(s): Hoang, Quoc
• Application Number:
  US15/604,747
• Publication Number:
  US 20170288051A1
• Time in Patent Office: 474 Days
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A recess is formed at a semiconductor layer of a device to define a plurality of mesas. An active trench portion of the recess residing between adjacent mesas. A termination portion of the trench residing between the end of each mesa and a perimeter of the recess. The transverse spacing between the mesas and the lateral spacing between the mesas and an outer perimeter of a recess forming the mesas are substantially the same. A shield structure within the trench extends from the region between the mesas to the region between the ends of the mesas and the outer perimeter of the recess forming the mesas. A contact resides between a shield electrode terminal and the shield portion residing in the trench.

Claims

1. A method of forming a vertical field effect transistor device, the method comprising:

providing a workpiece comprising a semiconductor layer;

forming a recess in the semiconductor layer to define a plurality of mesas spaced apart from an outer perimeter of the recess in a lateral direction by a first dimension, and spaced apart from each other by approximately the same dimension;

forming a shield region within the recess at a location concentric with to the outer perimeter and extending from the location coincident to the outer perimeter to locations between each pair of adjacent mesas;

forming a plurality of gates, each gate located between a corresponding pair of adjacent mesas having channel regions and overlying a portion of the shield region between each pair of adjacent mesas;

forming a dielectric over the workpiece after forming the plurality of gates;

forming a conductive plug opening corresponding to each mesa pair at a location that includes a point that is equidistant from an end of each mesa of the mesa pair and from the outer perimeter in the lateral direction, wherein

the conductive plug opening exposes a portion of the shield region, and

a center of the conductive plug opening is within 25% of a transverse dimension of the conductive plug opening from the point.

2. A method of forming a vertical field effect transistor device, the method comprising:

providing a workpiece comprising a semiconductor layer;

forming a recess in the semiconductor layer to define a plurality of mesas spaced apart from an outer perimeter of the recess in a lateral direction by a first dimension, and spaced apart from each other by approximately the same dimension;

forming a shield region within the recess at a location concentric with to the outer perimeter and extending from the location coincident to the outer perimeter to locations between each pair of adjacent mesas;

forming a plurality of gates, each gate located between a corresponding pair of adjacent mesas having channel regions and overlying a portion of the shield region between each pair of adjacent mesas;

forming a dielectric over the workpiece after forming the plurality of gates;

forming a conductive plug opening corresponding to each mesa pair at a location that includes a point that is equidistant from an end of each mesa of the mesa pair and from the outer perimeter in the lateral direction, wherein

the conductive plug opening exposes a portion of the shield region, and

a center of the conductive plug opening is greater than 10% of a transverse dimension of the conductive plug opening from the point.

3. A method of forming a vertical field effect transistor device, the method comprising:

providing a workpiece comprising a semiconductor layer;

forming a recess in the semiconductor layer to define a plurality of mesas spaced apart from an outer perimeter of the recess in a lateral direction by a first dimension, and spaced apart from each other by approximately the same dimension;

forming a shield region within the recess at a location concentric with to the outer perimeter and extending from the location coincident to the outer perimeter to locations between each pair of adjacent mesas;

forming a plurality of gates, each gate located between a corresponding pair of adjacent mesas having channel regions and overlying a portion of the shield region between each pair of adjacent mesas;

forming a dielectric over the workpiece after forming the plurality of gates;

forming a conductive plug opening corresponding to each mesa pair at a location that includes a point that is equidistant from an end of each mesa of the mesa pair and from the outer perimeter in the lateral direction, wherein

the conductive plug opening exposes a portion of the shield region, and

a transverse dimension of the shield region between each pair of adjacent mesas is less than or equal to one-and-a-half times a transverse dimension of the conductive plug opening.

4. A method of forming a vertical field effect transistor device, the method comprising:

providing a workpiece comprising a semiconductor layer;

forming a recess in the semiconductor layer to define a plurality of mesas spaced apart from an outer perimeter of the recess in a lateral direction by a first dimension, and spaced apart from each other by approximately the same dimension;

forming a shield region within the recess at a location concentric with to the outer perimeter and extending from the location coincident to the outer perimeter to locations between each pair of adjacent mesas;

forming a plurality of gates, each gate located between a corresponding pair of adjacent mesas having channel regions and overlying a portion of the shield region between each pair of adjacent mesas;

forming a dielectric over the workpiece after forming the plurality of gates;

forming a conductive plug opening corresponding to each mesa pair at a location that includes a point that is equidistant from an end of each mesa of the mesa pair and from the outer perimeter in the lateral direction, wherein

the conductive plug opening exposes a portion of the shield region, and

the conductive plug opening is a first conductive plug opening; and

forming a second conductive plug opening corresponding to each mesa pair simultaneous with the first conductive plug opening at a location between the mesas of the mesa pair, wherein the second conductive plug opening exposes a portion of the gate.

5. The method of claim 4, further comprising:

forming a first conductive region overlying the dielectric in contact with a first conductive plug formed in the first conductive plug opening; and

forming a second conductive region overlying the dielectric in contact with a second conductive plug formed in the second conductive plug opening.