Semiconductor device

• US 10,074,744 B2
• Filed: 06/16/2017
• Issued: 09/11/2018
• Est. Priority Date: 01/31/2014
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Numabe, Hideo, Shirai, Nobuyuki, Kato, Hirokazu, Uno, Tomoaki, Umezu, Kazuyuki
• Primary Examiner(s): Moore, Whitney T
• Assistant Examiner(s): Yi, Changhyun
• Application Number:
  US15/625,771
• Publication Number:
  US 20170288053A1
• Time in Patent Office: 452 Days
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/04034 Bonding areas specifically adapted for strap connectors
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05082 Two-layer arrangements
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/29101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/29339 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/37011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/371 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/37124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/37147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48137 : the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 : Fan-out arrangements
• CPC Class Codes: H01L 2224/73221 : Strap and wire connectors
• CPC Class Codes: H01L 2224/73263 : Layer and strap connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/83801 : Soldering or alloying
• CPC Class Codes: H01L 2224/84801 : Soldering or alloying
• CPC Class Codes: H01L 2224/8485 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 23/535 : including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/84 : using a strap connector
• CPC Class Codes: H01L 29/0696 : of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0865 : Disposition
• CPC Class Codes: H01L 29/0882 : Disposition
• CPC Class Codes: H01L 29/1033 : with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/407 : Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 : for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n⁺-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n⁺-type semiconductor region NR for a source.

Claims

1. A semiconductor device including a trench-gate type field effect transistor configuring a power transistor in a transistor formation region on a main surface of a semiconductor substrate, comprising:

a first trench formed in the transistor formation region of the semiconductor substrate;

a first electrode formed in a lower portion inside the first trench;

a gate electrode for the trench-gate type field effect transistor formed in an upper portion inside the first trench;

a first insulating film formed between the first electrode and a side wall and a bottom surface of the first trench;

a second insulating film formed between the gate electrode and the side wall of the first trench;

a third insulating film formed between the first electrode and the gate electrode;

a semiconductor region for a source of a first conductivity type formed in a region that is adjacent to the first trench in the semiconductor substrate, a semiconductor region for channel formation of a second conductivity type opposite to the first conductivity type positioned below the semiconductor region for a source, and a semiconductor region for a drain of the first conductivity type positioned below the semiconductor region for channel formation;

an interlayer insulating film formed on the main surface of the semiconductor substrate;

a wiring for a source formed on the interlayer insulating film and electrically connected to the semiconductor region for a source;

a wiring for a gate formed on the interlayer insulating film and electrically connected to the gate electrode; and

a first wiring formed on the interlayer insulating film and electrically connected to the first electrode,

wherein the first wiring is not connected to the wiring for a source through a conductor, and is not connected to the wiring for a gate through a conductor,

wherein the wiring for a source is arranged in the transistor formation region in plan view,

wherein the first wiring is formed on the interlayer insulating film in a periphery of the transistor formation region in plan view,

wherein the wiring for a gate is formed on the interlayer insulating film in a periphery of the transistor formation region in plan view, and

wherein the wiring for a gate is arranged between the wiring for a source and the first wiring in plan view.

2. The semiconductor device according to claim 1,

wherein a side surface of the gate electrode inside the first trench faces the semiconductor region for a source and the semiconductor region for channel formation through the second insulating film, and

a side surface and a bottom surface of the first electrode inside the first trench face the semiconductor region for a drain through the first insulating film.

3. The semiconductor device according to claim 1, further comprising:

a second trench formed in the semiconductor substrate in a periphery of the transistor formation region and connected to the first trench;

a contact hole for a gate formed in the interlayer insulating film in a region where the second trench and the wiring for a gate overlap with each other in plan view; and

a first contact hole formed in the interlayer insulating film in a region where the second trench and the first wiring overlap with each other in plan view,

wherein the second trench includes a first region in which the first electrode and the gate electrode are embedded and a second region in which the first electrode is embedded but the gate electrode is not embedded,

the first electrode is formed in a lower portion inside the second trench of the first region through the first insulating film, the gate electrode is formed in an upper portion inside the second trench of the first region through the second insulating film, and the third insulating film is formed between the first electrode and the gate electrode inside the second trench of the first region,

the first electrode is formed inside the second trench of the second region through the first insulating film,

the contact hole for a gate is formed above the second trench of the first region, and the wiring for a gate is electrically connected to the gate electrode exposed from the contact hole for a gate, and

the first contact hole is formed above the second trench of the second region, and the first wiring is electrically connected to the first electrode exposed from the first contact hole.

4. The semiconductor device according to claim 1,

wherein the wiring for a source is electrically connected to the semiconductor region for a source through a contact hole for a source formed in the interlayer insulating film.

5. The semiconductor device according to claim 1, further comprising:

a fourth insulating film formed on the interlayer insulating film so as to cover the wiring for a source, the wiring for a gate, and the first wiring,

wherein a pad for a source is formed by partially exposing the wiring for a source from an opening for a source of the fourth insulating film,

a pad for a gate is formed by partially exposing the wiring for a gate from an opening for a gate of the fourth insulating film, and

a first pad is formed by partially exposing the first wiring from a first opening of the fourth insulating film.

6. The semiconductor device according to claim 1,

wherein each of the wiring for a gate and the first wiring extends along an outer periphery of the wiring for a source.

7. The semiconductor device according to claim 1,

wherein the first trench extends in a first direction,

wherein the wiring for a gate includes a first wiring for a gate extending in a second direction which is perpendicular to the first direction, and extending along a first side of the main surface of the semiconductor device,

wherein the first wiring includes a first wiring portion extending in the second direction along the first side, and

wherein the first wiring portion is arranged between the first wiring portion for a gate and the first side in plan view.

8. The semiconductor device according to claim 7,

wherein a plurality of third trenches extending in the first direction are arranged so as to be spaced from each other in the second direction in a region where the first wiring portion for a gate and the first wiring portion extend along the first side,

a respective contact hole for a gate is formed in a region where the first wiring portion for a gate overlaps with each third trench extending in the first direction in plan view, and

a respective first contact hole is formed in a region where the first wiring portion overlaps with each third trench extending in the first direction in plan view.

9. The semiconductor device according to claim 7,

wherein a plurality of the first trenches extending in the first direction are arranged so as to be spaced from each other in the second direction in the transistor formation region.

10. The semiconductor device according to claim 9,

wherein the wiring for a gate includes a second wiring portion for a gate extending in the second direction along a second side facing the first side of the main surface of the semiconductor device,

the first wiring includes a second wiring portion extending in the second direction along the second side, and

the second wiring portion is arranged between the second wiring portion for a gate and the second side in plan view.