Printable inorganic semiconductor method

• US 10,074,768 B2
• Filed: 06/10/2016
• Issued: 09/11/2018
• Est. Priority Date: 05/15/2015
• Status: Active Grant

• Current Assignee: X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: X-Celeprint Limited
• Inventors: Meitl, Matthew, Cok, Ronald S.
• Primary Examiner(s): Booth, Richard
• Application Number:
  US15/179,380
• Publication Number:
  US 20170025563A1
• Time in Patent Office: 823 Days
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68322 Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 2933/0025 relating to coatings
• CPC Class Codes: H01L 2933/0033 relating to semiconductor body packages
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/26 Materials of the light emitting region
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/36 characterised by the electrodes
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/40 Materials therefor
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A method of making an inorganic semiconductor structure suitable for micro-transfer printing includes providing a growth substrate and forming one or more semiconductor layers on the growth substrate. A patterned release layer is formed on the conductor layer(s) and bonded to a handle substrate. The growth substrate is removed and the semiconductor layer(s) patterned to form a semiconductor mesa. A dielectric layer is formed and then patterned to expose first and second contacts and an entry portion of the release layer. A conductor layer is formed on the dielectric layer, the first contact, and the second contact and patterned to form a first conductor in electrical contact with the first contact and a second conductor in electrical contact with the second contact but electrically separate from the first conductor. At least a portion of the release layer is removed.

Claims

1. An inorganic semiconductor structure suitable for micro-transfer printing, comprising:

one or more semiconductor layers;

a conductor layer formed on the one or more semiconductor layers;

a patterned release layer formed on the conductor layer; and

a handle substrate bonded to the release layer,

wherein the conductor layer is in electrical contact with the one or more semiconductor layers over the extent of the one or more semiconductor layers,

wherein the one or more semiconductor layers comprise one or more light-emitting layers and a current-transport layer adjacent to the patterned release layer that extends beyond the one or more light-emitting layers.

3. The inorganic semiconductor structure of claim 1, wherein the one or more semiconductor layers include an n-doped semiconductor layer and a p-doped semiconductor layer formed on the n-doped semiconductor layer.

4. The inorganic semiconductor structure of claim 3, wherein the conductor layer is formed on the p-doped semiconductor layer.

5. The inorganic semiconductor structure of claim 1, comprising a growth substrate on which the one or more semiconductor layers are formed.

6. The inorganic semiconductor structure of claim 5, wherein the one or more semiconductor layers include an n-doped semiconductor layer and a p-doped semiconductor layer formed on the n-doped semiconductor layer, and the n-doped semiconductor layer is formed on the growth substrate.

2. An inorganic semiconductor structure suitable for micro-transfer printing, comprising:

one or more semiconductor layers;

a conductor layer formed on the one or more semiconductor layers;

a patterned release layer formed on the conductor layer; and

wherein the one or more semiconductor layers form a semiconductor mesa within the area defined by the patterned release layer;

wherein a portion of the conductor layer forms a conductor mesa beneath the semiconductor mesa that extends past at least one edge of the semiconductor mesa and exposes a portion of the patterned release layer around the conductor mesa.

16. The inorganic semiconductor structure of claim 2, comprising a dielectric layer on the exposed portion of the patterned release layer, the conductor mesa, and the semiconductor mesa.

17. The inorganic semiconductor structure of claim 16, wherein the dielectric layer is patterned to expose a first contact on the semiconductor mesa, a second contact on the conductor mesa, and an entry portion of the patterned release layer.

18. The inorganic semiconductor structure of claim 17, comprising a conductive layer on the patterned dielectric layer, the first contact, and the second contact.

19. The inorganic semiconductor structure of claim 18, wherein the conductive layer is patterned to form a first conductor in electrical contact with the first contact and a second conductor in electrical contact with the second contact, the first conductor electrically separate from the second conductor.

7. An inorganic semiconductor structure suitable for micro-transfer printing, comprising:

one or more semiconductor layers;

a conductor layer formed on the one or more semiconductor layers;

a patterned release layer formed on the conductor layer; and

wherein the one or more semiconductor layers form a semiconductor mesa within the area defined by the patterned release layer, and

wherein the conductor layer is in electrical contact with the one or more semiconductor layers over the extent of the one or more semiconductor layers,

wherein the one or more semiconductor layers comprise one or more light-emitting layers and a current-transport layer adjacent to the patterned release layer that extends beyond the one or more light-emitting layers.

8. The inorganic semiconductor structure of claim 7, wherein the one or more semiconductor layers include an n-doped semiconductor layer and a p-doped semiconductor layer formed on the n-doped semiconductor layer.

9. The inorganic semiconductor structure of claim 8, wherein the conductor layer is formed on the p-doped semiconductor layer.

10. The inorganic semiconductor structure of claim 7, comprising a handle substrate bonded to the patterned release layer.

11. An inorganic semiconductor structure suitable for micro-transfer printing, comprising:

one or more semiconductor layers and a conductor layer formed on the one or more semiconductor layers, wherein the one or more semiconductor layers form a semiconductor mesa and wherein a portion of the conductor layer forms a conductor mesa beneath the semiconductor mesa that extends past at least one edge of the semiconductor mesa;

a dielectric layer on exposed portions of the conductor mesa, and the semiconductor mesa, wherein the dielectric layer is patterned to expose a first contact on the semiconductor mesa and a second contact on the conductor mesa;

a conductive layer on the patterned dielectric layer, the first contact, and the second contact, wherein the conductive layer is patterned to form a first conductor in electrical contact with the first contact and a second conductor in electrical contact with the second contact, the first conductor electrically separate from the second conductor.

12. The inorganic semiconductor structure of claim 11, wherein the one or more semiconductor layers comprise one or more light-emitting layers and a current-transport layer that extends beyond the light-emitting layers and wherein the second contact is on the current-transport semiconductor layer.

13. The inorganic semiconductor structure of claim 11, wherein the one or more semiconductor layers include an n-doped semiconductor layer and a p-doped semiconductor layer formed on the n-doped semiconductor layer.

14. The inorganic semiconductor structure of claim 13, wherein the conductor layer is formed on the p-doped semiconductor layer.

15. The inorganic semiconductor structure of claim 14, wherein the conductor layer forms a first conductive sub-layer having first conductive materials on the p-doped semiconductor layer and a second conductive sub-layer having second conductive materials on the first conductive sub-layer.