High-frequency, high density power factor correction conversion for universal input grid interface

• US 10,075,064 B2
• Filed: 07/06/2015
• Issued: 09/11/2018
• Est. Priority Date: 07/03/2014
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Perreault, David J., Afridi, Khurram K., Santiago-Gonzalez, Juan A., Otten, David M.
• Primary Examiner(s): Moody, Kyle J
• Application Number:
  US14/791,685
• Publication Number:
  US 20160006365A1
• Time in Patent Office: 1,163 Days
• Field of Search: 363 16, 363 37, 363 44, 363123-127, 363143
• CPC Class Codes: H02M 1/14 Arrangements for reducing ripples from dc input or output
• CPC Class Codes: H02M 1/4208 Arrangements for improving power factor of AC input
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A circuit includes a reconfigurable rectifier, a voltage balancer, and a pair of converters. The reconfigurable rectifier includes an ac input port and three output ports. In a first configuration, the reconfigurable rectifier can deliver power at a first output port and, in a second configuration, to at least a second output port. The voltage balancer includes first and second ports coupled to second and third output ports of the reconfigurable rectifier and is configured to balance received voltage at the first and second ports. The first converter has an input coupled to the first port of the voltage balancer and an output at which a first converted voltage signal is provided. The second converter has an input coupled to the second port of the voltage balancer and an output at which a second converted voltage signal is provided.

Claims

1. A circuit comprising:

a reconfigurable rectifier having an input port configured to receive an alternating current (ac) input signal and first, second, and third output ports, wherein in a first configuration the reconfigurable rectifier is configured to deliver power at the first output port and in a second configuration the reconfigurable rectifier is configured to deliver power to at least the second output port;

a voltage balancer having first and second input ports and first and second output ports, with the first and second input ports of the voltage balancer coupled to the second and third output ports of the reconfigurable rectifier and configured to balance a voltage at the first and second output ports;

a first converter having an input coupled to the first port of the voltage balancer and having an output at which a first converted voltage signal is provided;

a second converter having an input coupled to the second port of the voltage balancer and having an output at which a second converted voltage signal is provided; and

wherein, in the second configuration, the reconfigurable rectifier is configured to deliver power to the second output port, wherein the voltage balancer is configured to transfer power received from the second output port of the reconfigurable rectifier such that the first and second converters may process substantially equal power levels.

2. The circuit of claim 1 wherein, in the second configuration, the reconfigurable rectifier is configured to deliver power to the second and third output ports in alternating half ac cycles, wherein the voltage balancer is configured to transfer power received from the second and third output ports of the reconfigurable rectifier such that the first and second converters may process substantially equal power levels.

3. The circuit of claim 1 further comprising at least one configuration switch having a first state to place the reconfigurable rectifier in the first configuration and a second state to place the reconfigurable rectifier in the second configuration.

4. The circuit of claim 1 further comprising a controller, wherein in response to a value of the ac input signal, the controller places the configuration switch in the first or second state.

5. The circuit of claim 1 wherein the first and second converters are provided as buck converters.

6. The circuit of claim 5 wherein the first converter is provided as a resonant-transition buck converter and the second converter is provided as an inverted resonant-transition buck converter.

7. The circuit of claim 1 further comprising an energy buffer circuit network having an input coupled to the outputs of the first and second converters and at least one energy storage element, the energy buffer circuit network configured to provide buffering of twice-line-frequency energy.

8. The circuit of claim 7 wherein the outputs of the first and second converters are connected such that the energy buffer circuit network appears across the sum of the output voltages of the first and second converters.

9. The circuit of claim 7 wherein the at least one energy storage element comprises at least one capacitor.

10. The circuit of claim 7 wherein the energy buffer circuit network comprises three capacitors connected in a delta fashion.

11. A circuit comprising:

a reconfigurable rectifier having an input port configured to receive an alternating current (ac) input signal and first, second, and third output ports, wherein in a first configuration the reconfigurable rectifier is configured to deliver power at the first output port and in a second configuration the reconfigurable rectifier is configured to deliver power to at least the second output port;

a voltage balancer having first and second input ports and first and second output ports, with the first and second input ports of the voltage balancer coupled to the second and third output ports of the reconfigurable rectifier and configured to balance a voltage at the first and second output ports;

a first converter having an input coupled to the first port of the voltage balancer and having an output at which a first converted voltage signal is provided;

a second converter having an input coupled to the second port of the voltage balancer and having an output at which a second converted voltage signal is provided; and

wherein, in the second configuration, the reconfigurable rectifier is configured to deliver power to the second and third output ports in alternating half ac cycles, wherein the voltage balancer is configured to transfer power received from the second and third output ports of the reconfigurable rectifier such that the first and second converters may process substantially equal power levels.

12. The circuit of claim 11 wherein, in the second configuration, the reconfigurable rectifier is configured to deliver power to the second output port, wherein the voltage balancer is configured to transfer power received from the second output port of the reconfigurable rectifier such that the first and second converters may process substantially equal power levels.

13. The circuit of claim 11 further comprising at least one configuration switch having a first state to place the reconfigurable rectifier in the first configuration and a second state to place the reconfigurable rectifier in the second configuration.

14. The circuit of claim 11 further comprising a controller, wherein in response to a value of the ac input signal, the controller places the configuration switch in the first or second state.

15. The circuit of claim 11 wherein the first and second converters are provided as buck converters.

16. The circuit of claim 15 wherein the first converter is provided as a resonant-transition buck converter and the second converter is provided as an inverted resonant-transition buck converter.

17. The circuit of claim 11 further comprising an energy buffer circuit network having an input coupled to the outputs of the first and second converters and at least one energy storage element, the energy buffer circuit network configured to provide buffering of twice-line-frequency energy.

18. The circuit of claim 17 wherein the outputs of the first and second converters are connected such that the energy buffer circuit network appears across the sum of the output voltages of the first and second converters.

19. The circuit of claim 17 wherein the at least one energy storage element comprises at least one capacitor.

20. The circuit of claim 17 wherein the energy buffer circuit network comprises three capacitors connected in a delta fashion.