Continuous time linear equalizer with two adaptive zero frequency locations
First Claim
Patent Images
1. A continuous-time linear equalizer device comprising:
- a first input terminal;
a second input terminal;
a first input transistor comprising a first gate terminal a first drain terminal and a first source terminal, the first gate terminal being coupled to the first input signal;
a second input transistor comprising a second gate terminal a second drain terminal and a second source terminal, the second gate terminal being coupled to the second input signal;
a first source resistor coupled to the first source terminal;
a second source resistor coupled to the first source resistor and the second source terminal;
a first terminal positioned between the first source resistor and the second source resistor;
a first source capacitor coupled to the first source terminal;
a second source capacitor coupled to the second source terminal;
a second terminal positioned between the first source capacitor and the second source capacitor and coupled to the first terminal;
a first compensation circuit coupled to the first drain terminal, the first compensation circuit comprising a first load capacitor and a first load resistor, the first load capacitor and the first load resistor being associated with a predetermined low-frequency zero; and
a first gain tuning circuit coupled to the first compensation circuit.
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Abstract
The present invention is directed to electrical circuits. More specifically, embodiments of the presentation provide a CTLE module that includes a two compensation sections. A high-frequency zero RC section is in the source of the differential pair and close to the bias current source. A low-frequency zero section is coupled to an output terminal and configured outside the input signal path. A DC gain tuning section is coupled to the low-frequency zero section. There are other embodiments as well.
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Citations
19 Claims
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1. A continuous-time linear equalizer device comprising:
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a first input terminal; a second input terminal; a first input transistor comprising a first gate terminal a first drain terminal and a first source terminal, the first gate terminal being coupled to the first input signal; a second input transistor comprising a second gate terminal a second drain terminal and a second source terminal, the second gate terminal being coupled to the second input signal; a first source resistor coupled to the first source terminal; a second source resistor coupled to the first source resistor and the second source terminal; a first terminal positioned between the first source resistor and the second source resistor; a first source capacitor coupled to the first source terminal; a second source capacitor coupled to the second source terminal; a second terminal positioned between the first source capacitor and the second source capacitor and coupled to the first terminal; a first compensation circuit coupled to the first drain terminal, the first compensation circuit comprising a first load capacitor and a first load resistor, the first load capacitor and the first load resistor being associated with a predetermined low-frequency zero; and a first gain tuning circuit coupled to the first compensation circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A continuous-time linear equalizer device comprising:
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a first input terminal; a second input terminal; a first input transistor comprising a first gate terminal a first drain terminal and a first source terminal, the first gate terminal being coupled to the first input signal; a second input transistor comprising a second gate terminal a second drain terminal and a second source terminal, the second gate terminal being coupled to the second input signal; a first source resistor coupled to the first source terminal; a second source resistor coupled to the first source resistor and the second source terminal; a first terminal positioned between the first source resistor and the second source resistor; a first source capacitor coupled to the first source terminal; a second source capacitor coupled to the second source terminal; a second terminal positioned between the first source capacitor and the second source capacitor and coupled to the first terminal; a first compensation circuit coupled to the first drain terminal, the first compensation circuit comprising a first load capacitor and a first load resistor, the first load capacitor and the first load resistor being associated with a predetermined low-frequency zero. - View Dependent Claims (17)
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18. A continuous-time linear equalizer device comprising:
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a first input transistor comprising a first gate terminal a first drain terminal and a first source terminal, the first gate terminal being coupled to a first input signal; a second input transistor comprising a second gate terminal a second drain terminal and a second source terminal, the second gate terminal being coupled to a second input signal; a first source resistor coupled to the first source terminal; a second source resistor coupled to the first source resistor and the second source terminal; a first terminal positioned between the first source resistor and the second source resistor; a first source capacitor coupled to the first source terminal; a second source capacitor coupled to the second source terminal; a second terminal positioned between the first source capacitor and the second source capacitor and coupled to the first terminal; a first compensation circuit coupled to the first drain terminal, the first compensation circuit comprising a first load capacitor and a first load resistor, the first load capacitor and the first load resistor being associated with a predetermined low-frequency zero; and a second compensation circuit coupled to the second source terminal. - View Dependent Claims (19)
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Specification