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Pulse width modulation (PWM) to align clocks across multiple separated cards within a communication system

  • US 10,075,284 B1
  • Filed: 11/30/2016
  • Issued: 09/11/2018
  • Est. Priority Date: 01/21/2016
  • Status: Active Grant
First Claim
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1. A method for phase alignment of a clock signal at a plurality of line cards, the method comprising:

  • receiving a pulse-width modulated (PWM) clock signal from each of the plurality of line cards at a timing device;

    monitoring each of the PWM clock signals from each of the plurality of line cards;

    locking a first digital phase-locked loop (DPLL) circuit to a highest priority PWM clock signal that is not experiencing a failure to generate a PWM clock output signal;

    determining a propagation delay for each of a plurality of line cards following a round-robin approach at the timing device, the timing device coupled to each of the plurality of line cards over a backplane;

    determining, at the timing device, a phase delay correction for each of the plurality of line cards based upon the determined propagation delay for each of the plurality of line cards;

    encoding the phase delay correction for each of the plurality of line cards into the PWM clock output signal to generate a phase delay correction encoded PWM clock output signal for each of the plurality of line cards; and

    transmitting the phase delay correction encoded PWM clock output signal to each of the plurality of line cards following the round-robin approach.

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