Pulse width modulation (PWM) to align clocks across multiple separated cards within a communication system

• US 10,075,284 B1
• Filed: 11/30/2016
• Issued: 09/11/2018
• Est. Priority Date: 01/21/2016
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Rodrigues, Silvana, Rupert, Michael, Baidas, Zaher, Goldin, Leon
• Primary Examiner(s): Fan, Chieh M
• Assistant Examiner(s): Hailegiorgis, Fitwi
• Application Number:
  US15/364,602
• Time in Patent Office: 650 Days
• Field of Search: 375371, 375356, 710310
• CPC Class Codes: H04J 3/0688 Change of the master or reference, e.g. take-over or failure of the master
• CPC Class Codes: H04J 3/0697 Synchronisation in a packet node
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A system and method for clock phase alignment at a plurality of line cards over a backplane of a communication system. Phase adjustments are continually made for the clock signals at the line cards by dynamically measuring the propagation delay between the timing device and each of the plurality of line cards and continuously communicating the appropriate phase adjustment to each of the plurality of line cards.

Claims

1. A method for phase alignment of a clock signal at a plurality of line cards, the method comprising:

receiving a pulse-width modulated (PWM) clock signal from each of the plurality of line cards at a timing device;

monitoring each of the PWM clock signals from each of the plurality of line cards;

locking a first digital phase-locked loop (DPLL) circuit to a highest priority PWM clock signal that is not experiencing a failure to generate a PWM clock output signal;

determining a propagation delay for each of a plurality of line cards following a round-robin approach at the timing device, the timing device coupled to each of the plurality of line cards over a backplane;

determining, at the timing device, a phase delay correction for each of the plurality of line cards based upon the determined propagation delay for each of the plurality of line cards;

encoding the phase delay correction for each of the plurality of line cards into the PWM clock output signal to generate a phase delay correction encoded PWM clock output signal for each of the plurality of line cards; and

transmitting the phase delay correction encoded PWM clock output signal to each of the plurality of line cards following the round-robin approach.

2. A method for phase alignment of a clock signal at a plurality of line cards, the method comprising:

generating a pulse-width modulated (PWM) clock output signal at a timing device;

transmitting a timing signal over a first backplane trace from the timing device to each of the plurality of line cards, the timing device coupled to each of the plurality of line cards over a backplane;

receiving, at the timing device, a return timing signal from each of the plurality of line cards over a second backplane trace;

measuring a round-trip delay time associated with each of the plurality of line cards using a ranging algorithm and the return timing signal;

dividing the round-trip delay time associated with each of the plurality of line cards by half to determine the propagation delay for each of the plurality of line cards;

determining, at the timing device, a phase delay correction for each of the plurality of line cards based upon the determined propagation delay for each of the plurality of line cards;

encoding the phase delay correction for each of the plurality of line cards into the PWM clock output signal to generate a phase delay correction encoded PWM clock output signal for each of the plurality of line cards; and

transmitting the phase delay correction encoded PWM clock output signal to each of the plurality of line cards following the round-robin approach.

3. The method of claim 2, wherein the round-robin approach comprises sequentially accessing each of the plurality of line cards using a multiplexer of the timing device.

4. A method for phase alignment of a clock signal at a plurality of line cards, the method comprising:

generating a pulse-width modulated (PWM) clock output signal at a timing device that is coupled to each of the plurality of line cards over a backplane;

transmitting a timing signal over a bidirectional backplane trace from the timing device to each of the plurality of line cards;

receiving, at the timing device, a return timing signal from each of the plurality of line cards over the bidirectional backplane trace;

measuring a time difference between transmitting the timing signal and receiving the return timing signal from each of the plurality of line cards using a ping-pong algorithm to determine a propagation delay for each of the plurality of line cards;

determining, at the timing device, a phase delay correction for each of the plurality of line cards based upon the determined propagation delay for each of the plurality of line cards;

encoding the phase delay correction for each of the plurality of line cards into the PWM clock output signal to generate a phase delay correction encoded PWM clock output signal for each of the plurality of line cards; and

transmitting the phase delay correction encoded PWM clock output signal to each of the plurality of line cards following the round-robin approach.

5. The method of claim 4, wherein the round-robin approach comprises sequentially accessing each of the plurality of line cards using Time Division Multiplexing (TDM) on the bidirectional backplane trace.

6. A method for phase alignment of a clock signal at a plurality of line cards, the method comprising:

generating a pulse-width modulated (PWM) clock output signal at a timing device;

decoding a return clock signal from each of the plurality of line cards prior to determining a propagation delay for each of a plurality of line cards following a round robin approach at the timing device, the timing device coupled to each of the plurality of line cards over a backplane;

determining the propagation delay for each of the plurality of line cards following the round-robin approach at the timing device;

determining, at the timing device, a phase delay correction for each of the plurality of line cards based upon the determined propagation delay for each of the plurality of line cards;

encoding the phase delay correction for each of the plurality of line cards into the PWM clock output signal to generate a phase delay correction encoded PWM clock output signal for each of the plurality of line cards;

transmitting the phase delay correction encoded PWM clock output signal to each of the plurality of line cards following the round-robin approach.

7. A method for phase alignment of a clock signal at a plurality of line cards, the method comprising:

generating a pulse-width modulated (PWM) clock output signal at a timing device;

determining a propagation delay for each of a plurality of line cards following a round-robin approach at the timing device, the timing device coupled to each of the plurality of line cards over a backplane;

determining, at the timing device, a phase delay correction for each of the plurality of line cards based upon the determined propagation delay for each of the plurality of line cards;

encoding the phase delay correction for each of the plurality of line cards into the PWM clock output signal to generate a phase delay correction encoded PWM clock output signal for each of the plurality of line cards;

assigning a specific address to each of the plurality of line cards and encoding the specific address of each of the plurality of line cards into the phase delay correction encoded PWM clock output signal; and

transmitting the phase delay correction encoded PWM clock output signal to each of the plurality of line cards following the round-robin approach.

8. A timing device for performing phase alignment of a clock signal at a plurality of line cards, the timing device comprising:

a first multiplexer for receiving a PWM clock signal from each of the plurality of line cards;

a first digital phase-locked loop (DPLL) circuit coupled to the first multiplexer, for monitoring each of the PWM clock signals from each of the plurality of line cards and for locking the first DPLL circuit to a highest priority PWM clock signal that is not experiencing a failure to generate a pulse-width modulated (PWM) clock output signal;

a processor implementing an algorithm for determining a propagation delay for each of the plurality of line cards following a round-robin approach;

a second DPLL circuit for determining a phase delay correction for each of the plurality of line cards based upon the determined propagation delay for each of the plurality of line cards; and

an PWM encoder coupled to the first DPLL circuit and to the second DPLL circuit, the PWM encoder for encoding the phase delay correction for each of the plurality of line cards into the PWM clock output signal to generate a phase delay correction encoded PWM clock output signal to be transmitted to each of the plurality of line cards.

9. A timing device for performing phase alignment of a clock signal at a plurality of line cards, the timing device comprising:

a first digital phase-locked loop (DPLL) circuit for generating a pulse-width modulated (PWM) clock output signal, wherein the first DPLL circuit is further for transmitting a PWM timing signal over a first backplane trace from the timing device to each of the plurality of line cards;

a processor implementing an algorithm for determining a propagation delay for each of the plurality of line cards following a round-robin approach;

a second DPLL circuit for determining a phase delay correction for each of the plurality of line cards based upon the determined propagation delay for each of the plurality of line cards;

a second multiplexer coupled to the second DPLL circuit and to the processor, the second multiplexer for receiving, a PWM return timing signal from each of the plurality of line cards over a second backplane trace;

an PWM encoder coupled to the first DPLL circuit and to the second DPLL circuit, the PWM encoder for encoding the phase delay correction for each of the plurality of line cards into the PWM clock output signal to generate a phase delay correction encoded PWM clock output signal to be transmitted to each of the plurality of line cards; and

wherein the algorithm implemented by the processor is a ranging algorithm for measuring a round-trip delay time associated with each of the plurality of line cards based on the PWM return timing signal and for dividing the round-trip delay time associated with each of the plurality of line cards by half to determine the propagation delay for each of the plurality of line cards.

10. The timing device of claim 9, wherein the round-robin approach is implemented by the processor and comprises sequentially accessing each of the plurality of line cards using the second multiplexer.

11. A timing device for performing phase alignment of a clock signal at a plurality of line cards, the timing device comprising:

a first digital phase-locked loop (DPLL) circuit for generating a pulse-width modulated (PWM) clock output signal wherein the first DPLL circuit is further for transmitting a timing signal over a bidirectional backplane trace from the timing device to each of the plurality of line cards;

a processor implementing an algorithm for determining a propagation delay for each of the plurality of line cards following a round-robin approach;

a second DPLL circuit for determining a phase delay correction for each of the plurality of line cards based upon the determined propagation delay for each of the plurality of line cards;

an PWM encoder coupled to the first DPLL circuit and to the second DPLL circuit, the PWM encoder for encoding the phase delay correction for each of the plurality of line cards into the PWM clock output signal to generate a phase delay correction encoded PWM clock output signal to be transmitted to each of the plurality of line cards;

a switching circuit for receiving a return timing signal from each of the plurality of line cards over the bidirectional backplane trace; and

wherein the algorithm implemented by the processor is a ping-pong algorithm for measuring a time difference between transmitting the timing signal and receiving the return timing signal from each of the plurality of line cards to determine the propagation delay for each of the plurality of line cards.

12. The timing device of claim 11, wherein the round-robin approach is implemented by the processor and comprises sequentially accessing each of the plurality of line cards using Time Division Multiplexing (TDM) on the bidirectional backplane trace.

13. A timing device for performing phase alignment of a clock signal at a plurality of line cards, the timing device comprising:

a first digital phase-locked loop (DPLL) circuit for generating a pulse-width modulated (PWM) clock output signal;

a PWM decoder for decoding a return clock signal from each of the plurality of line cards prior to determining a propagation delay for each of a plurality of line cards following a round robin approach at the timing device;

a processor implementing an algorithm for determining the propagation delay for each of the plurality of line cards following the round-robin approach;

a second DPLL circuit coupled to the PWM decoder for determining a phase delay correction for each of the plurality of line cards based upon the determined propagation delay for each of the plurality of line cards;

an PWM encoder coupled to the first DPLL circuit and to the second DPLL circuit the PWM encoder for encoding the phase delay correction for each of the plurality of line cards into the PWM clock output signal to generate a phase delay correction encoded PWM clock output signal to be transmitted to each of the plurality of line cards.

14. A timing device for performing phase alignment of a clock signal at a plurality of line cards, the timing device comprising:

a first digital phase-locked loop (DPLL) circuit for generating a pulse-width modulated (PWM) clock output signal;

a processor implementing an algorithm for determining a propagation delay for each of the plurality of line cards following a round-robin approach, wherein the processor is further configured for, assigning a specific address to each of the plurality of line cards;

a second DPLL circuit for determining a phase delay correction for each of the plurality of line cards based upon the determined propagation delay for each of the plurality of line cards; and

an PWM encoder coupled to the first DPLL circuit and to the second DPLL circuit, the PWM encoder for encoding the phase delay correction for each of the plurality of line cards into the PWM clock output signal to generate a phase delay correction encoded PWM clock output signal to be transmitted to each of the plurality of line cards, and the PWM encoder further configured for encoding the specific address of each of the plurality of line cards into the phase delay correction encoded PWM clock output signal.