Short circuit detecting device of stacked memory chips and method thereof

• US 10,078,110 B2
• Filed: 10/17/2016
• Issued: 09/18/2018
• Est. Priority Date: 01/28/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yun, Won-Joo, Kang, Sukyong, Yu, Hye-Seung, Lee, Hyunui
• Primary Examiner(s): Astacio-Oquendo, Giovanni
• Application Number:
  US15/295,244
• Publication Number:
  US 20170219647A1
• Time in Patent Office: 701 Days
• Field of Search: 324500, 324537, 32476201
• CPC Class Codes: G01R 31/26 Testing of individual semiconductor devices testing or measuring during manufacture or treatment H01L22/00; testing of photovoltaic devices H02S50/10
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors

Abstract

Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

Claims

1. A short circuit detecting circuit comprising:

a plurality of data input/output pads each connected to respective ones of a plurality of micro-bumps;

a plurality of data output circuits each including a pull-up driver and a pull-down driver, the plurality of data output circuits each configured to drive respective ones of the plurality of data input/output pads;

a pull-up driver output control circuit configured to select, for each of the plurality of data output circuits, one of an off state, a weak-on state, and a strong-on state as an output of the pull-up driver associated therewith based on a micro-bump short circuit test type;

a pull-down driver output control circuit configured to select, for each of the plurality of data output circuits, one of the off state, the weak-on state, and the strong-on state as an output of the pull-down driver associated therewith based on the micro-bump short circuit test type;

a test input data storage circuit; and

a test output data storage circuit.

2. The short circuit detecting circuit of claim 1, wherein the micro-bump short circuit test type comprises at least one of (i) an operation of testing a short circuit between one of the plurality of micro-bumps and a ground voltage, (ii) an operation of testing a short circuit between one of the plurality of micro-bumps and a power supply voltage, and (iii) an operation of testing a short circuit between adjacent ones of the plurality of micro-bumps.

3. The short circuit detecting circuit of claim 2, wherein if the micro-bump short circuit test type is the operation of testing the short circuit between the one of the plurality of micro-bumps and the ground voltage, the pull-up driver output control circuit is configured to set an output of the pull-up driver of each of the plurality of data output circuits to the weak-on state, and the pull-down driver output control circuit is configured to set the output of the pull-down driver of each of the plurality of data output circuits to the off state.

4. The short circuit detecting circuit of claim 2, wherein if the micro-bump short circuit test type is the operation of testing the short circuit between the one of the micro-bumps and the power supply voltage, the pull-up driver output control circuit is configured to set an output of the pull-up driver of each of the plurality of data output circuits to the off state, and the pull-down driver output control circuit is configured to set an output of the pull-down driver of each of the plurality of data output circuits to the weak-on state.

5. The short circuit detecting circuit of claim 2, wherein if the micro-bump short circuit test type is the operation of testing the short circuit between the adjacent ones of the plurality of micro-bumps,

the pull-up driver output control circuit is configured to,

set an output of the pull-up driver connected to a micro-bump corresponding to a short circuit test target to the weak-on state, and

set an output of the pull-up driver connected to a micro-bump adjacent to the micro-bump corresponding to the short circuit test target to the off state;

and

the pull-down driver output control circuit is configured to,

set an output of the pull-down driver connected to the micro-bump corresponding to the short circuit test target to the off state,

set an output of the pull-down driver connected to the micro-bump adjacent to the micro-bump corresponding to the short circuit test target to the strong-on state.

6. The short circuit detecting circuit of claim 2, wherein if the micro-bump short circuit test type is the operation of testing the short circuit between the adjacent micro-bumps,

the pull-up driver output control circuit is configured to,

set an output of the pull-up driver connected to a micro-bump corresponding to a short circuit test target to the off state, and

set an output of the pull-up driver connected to a micro-bump adjacent to the micro-bump corresponding to the short circuit test target to the strong-on state;

and

the pull-down driver output control circuit is configured to,

set an output of the pull-down driver connected to the micro-bump corresponding to the short circuit test target to the weak-on state, and

set an output of the pull-down driver connected to the micro-bump adjacent to the micro-bump corresponding to the short circuit test target to the weak-on state.

7. The short circuit detecting circuit of claim 1, wherein the pull-up driver output control circuit is configured to,

set an output of each of the pull-up drivers such that the plurality of data output circuits perform a normal data output operation in a first operation mode, and

set an output of each of the pull-up drivers such that the plurality of the data output circuits perform a micro-bump short circuit test operation in a second operation mode.

8. The short circuit detecting circuit of claim 7, wherein the second operation mode is a mode register set (MRS) operation.

9. The short circuit detecting circuit of claim 7, wherein the pull-up driver output control circuit is configured to generate a plurality of pull-up output control signals to set outputs of respective ones of the pull-up drivers.

10. The short circuit detecting circuit of claim 1, wherein the pull-down driver output control circuit is configured to,

set an output of the pull-down drivers such that the plurality of data output circuits perform a normal data output operation in a first operation mode, and

set an output of the pull-down drivers such that the plurality of data output circuits perform a micro-bump short circuit test operation in a second operation mode.

11. The short circuit detecting circuit of claim 10, wherein the second operation mode is a mode register set (MRS) operation.

12. The short circuit detecting circuit of claim 10, wherein the pull-down driver output control circuit generates a plurality of pull-down output control signals to set outputs of respective ones of the pull-down drivers.

13. The short circuit detecting circuit of claim 1, wherein each of the pull-up drivers comprise:

a plurality of pull-up elements, the plurality of pull-up elements configured to turn off or on based on pull-up output control signals from the pull-up driver output control circuit.

14. The short circuit detecting circuit of claim 1, wherein each of the pull-down drivers comprise:

a plurality of pull-down elements configured to turn off or on based on pull-down output control signals from the pull-down driver output control circuit.

15. The short circuit detecting circuit of claim 1, wherein the test input data storage circuit comprises:

an m-stage shift register including m registers connected in series, where “

m”

is a number of the plurality of micro-bumps of a semiconductor chip to be tested to detect a micro-bump short circuit.

16. The short circuit detecting circuit of claim 15, wherein the test input data storage circuit is configured to,

sequentially receive test input data to a first register of the m-stage shift register during m clock cycles, and

shift the test input data stored in the first register into a next register of the m-stage shift register every rising transition of a clock signal.

17. The short circuit detecting circuit of claim 15, wherein the plurality of data output circuits are each configured to receive an output of a corresponding register of the m-stage shift register.

18. The short circuit detecting circuit of claim 1, wherein the test output data storage circuit comprises:

an m-stage shift register including m registers connected in series, where “

m”

is a number of the plurality of micro-bumps of a semiconductor chip to be tested to detect a micro-bump short circuit.

19. The short circuit detecting circuit of claim 18, wherein the test output data storage circuit is configured to,

sequentially output test output data to an m-th register of the m-stage shift register of the test output data storage circuit during m clock cycles, and

shift the test output data stored in the m-th register into a next register of the m-stage shift register every rising transition of a clock signal.

20. A semiconductor package comprising:

a first semiconductor device having a plurality of micro-bumps on an active surface thereof and a plurality of bulk bumps on an inactive surface thereof, the plurality of bulk bumps connected through-silicon vias to the plurality of micro-bumps; and

a second semiconductor device vertically stacked on the first semiconductor device and connected to the first semiconductor device via the plurality of micro-bumps;

the second semiconductor device having a short circuit detecting circuit including,

a plurality of data input/output pads each connected to respective ones of the plurality of micro-bumps,

a plurality of data output circuits each including a pull-up driver and a pull-down driver, the plurality of data output circuits each configured to drive respective ones of the plurality of data input/output pads,

a pull-up driver output control circuit configured to select, for each of the plurality of data output circuits, one of an off state, a weak-on state, and a strong-on state as an output of the pull-up driver associated therewith based on a micro-bump short circuit test type;

a pull-down driver output control circuit configured to select, for each of the plurality of data output circuits, one of the off state, the weak-on state, and the strong-on state as an output of the pull-down driver associated therewith based on the micro-bump short circuit test type;

a test input data storage circuit; and

a test output data storage circuit.