Memory activity driven adaptive performance measurement

• US 10,078,447 B2
• Filed: 11/05/2015
• Issued: 09/18/2018
• Est. Priority Date: 08/31/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chinnakkonda Vidyapoornachary, Diyanesh B., Purushotham, Srinivas B.
• Primary Examiner(s): Bertram, Ryan
• Assistant Examiner(s): Ta, Trang Khanh
• Application Number:
  US14/933,575
• Publication Number:
  US 20170060423A1
• Time in Patent Office: 1,048 Days
• CPC Class Codes: G06F 1/20 Cooling means
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/027 in fuses
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.

Claims

1. A method of monitoring memory performance, the method comprising:

selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register;

monitoring memory accesses to the selected portion of memory during a first sampling period;

selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period;

monitoring memory accesses to the different portion of memory during the subsequent sampling period;

recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods;

generating one or more interrupts to output data regarding the monitored memory accesses during the first sampling period and during the subsequent sampling period for workload and usage data analysis; and

analyzing, using the workload and usage data analysis, how the memory modules behave when peak bandwidth workload is run and how power management is handled when low workload bandwidth is run.

2. The method of claim 1, wherein selecting the first portion of memory comprises:

determining which of the two or more portions of memory has the highest number of memory accesses during a given time window; and

selecting the portion of memory having the highest number of memory accesses;

wherein the different portion of memory is selected in response to determining that the respective number of memory accesses of the different portion of memory has subsequently increased such that the different portion of memory has more memory accesses than the first portion of memory.

3. The method of claim 1, wherein selecting the first portion of memory comprises:

determining which of the two or more portions of memory has the lowest number of memory accesses during a given time window; and

selecting the portion of memory having the lowest number of memory accesses;

wherein the different portion of memory is selected in response to determining that the respective number of memory accesses of the different portion of memory is subsequently lower than the number of memory accesses of the first portion of memory.

4. The method of claim 1, wherein selecting the different portion of memory for monitoring in the subsequent sampling period comprises selecting each of the two or more portions of memory in a respective subsequent sampling period such that each of the two or more portions is monitored in a round robin fashion.

5. The method of claim 1, wherein generating the one or more interrupts comprises generating each interrupt at predetermined time intervals.

6. The method of claim 1, wherein generating the one or more interrupts comprises generating each interrupt when a counter configured to count the number of memory accesses has reached a predetermined limit.

7. The method of claim 1, wherein each of the two or more portions of memory comprises one of a rank of a memory module coupled to a memory controller, a bank of a memory module coupled to a memory controller, or a memory buffer in a memory controller.

8. The method of claim 1, further comprising:

monitoring traffic access patterns for each portion of memory.

9. The method of claim 1, wherein the first sampling period and the subsequent sampling period are defined by one or more user inputs.

10. The method of claim 1, wherein the subsequent sampling period is defined dynamically based on the monitoring of memory accesses to the selected portion of memory during the first sampling period.

11. The method of claim 1, wherein the control register contains configuration bits in an adaptive mode field, a rank select field, a bank select field, and a device level select field.

12. The method of claim 1, further comprising:

modifying, based on the usage data analysis, a memory subsystem which contains the two or more portions of memory by adjusting an amount of energy supplied to one or more portions of the memory sub-system.

13. The method of claim 1, wherein the developing the detailed memory characterization for both the peak bandwidth driving workload and the low bandwidth workload further comprises developing a rank level stress distribution across the two or more portions of memory.

14. The method of claim 1, wherein the developing the detailed memory characterization for both the peak bandwidth driving workload and the low bandwidth workload further comprises collecting data regarding how power management is handled when a low workload bandwidth is run.