Apparatus and method for accelerating operations in a processor which uses shared virtual memory

• US 10,078,519 B2
• Filed: 07/27/2016
• Issued: 09/18/2018
• Est. Priority Date: 03/30/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Weissmann, Eliezer, Vaithianathan, Karthikeyan Karthik, Zach, Yoav, Ginzburg, Boris, Ronen, Ronny
• Primary Examiner(s): Nguyen, Hiep
• Application Number:
  US15/221,557
• Publication Number:
  US 20160335090A1
• Time in Patent Office: 783 Days
• Field of Search: 711117, 711156, 711159, 711207, 710 58, 710 64, 710120
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1045 associated with a data cache
• CPC Class Codes: G06F 12/1072 Decentralised address translation, e.g. in distributed shared memory systems
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/302 In image processor or graphics adapter
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 2212/65 Details of virtual memory and virtual address translation
• CPC Class Codes: G06F 2212/68 Details of translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/683 Invalidation
• CPC Class Codes: G06F 2212/684 : TLB miss handling
• CPC Class Codes: G06F 3/0646 : Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
• CPC Class Codes: G06F 3/0662 : Virtualisation aspects
• CPC Class Codes: G06F 3/0668 : adopting a particular infrastructure
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3881 : Arrangements for communication of instructions and data
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]

Abstract

An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

Claims

1. A system comprising:

one or more simultaneous multithreading (SMT) cores, one or more of the SMT cores perform out-of-order instruction execution for a plurality of threads;

a memory subsystem comprising a system memory and a plurality of cache levels communicatively coupled to one or more of the SMT cores; and

an accelerator communicatively coupled to one or more of the cores and the memory subsystem, the accelerator comprising;

a memory management circuit to attempt a virtual-to-physical address translation by querying a translation lookaside buffer (TLB) containing a mapping of virtual-to-physical addresses,

the memory management circuit to access a page table from the memory subsystem to perform the translation if the query to the TLB fails to locate a translation for a particular virtual address;

a memory interface circuit to interconnect the accelerator to the memory subsystem, the memory interface circuit to access the memory subsystem using the address translation provided by the memory management circuit; and

execution circuitry to execute instructions and process data retrieved from the memory subsystem.

2. The system as in claim 1 wherein the plurality of cache levels include a first cache integral to at least one SMT core and a second cache to be shared by two or more of the SMT cores.

3. The system as in claim 2 wherein at least one of the SMT cores comprises:

an instruction fetch circuit to fetch instructions of one or more threads;

an instruction decode circuit to decode the instructions;

a register renaming circuit to rename registers of a register file;

an instruction cache circuit to store instructions to be executed;

a data cache circuit to store data;

at least one level 2 (L2) cache circuit to store both instructions and data and communicatively coupled to the instruction cache circuit and the data cache circuit.