Resistive memory device for matrix-vector multiplications

• US 10,079,058 B1
• Filed: 08/24/2017
• Issued: 09/18/2018
• Est. Priority Date: 08/24/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Eleftheriou, Evangelos S., Le Gallo-Bourdeau, Manuel, Sebastian, Abu
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US15/685,788
• Time in Patent Office: 390 Days
• Field of Search: 365148
• CPC Class Codes: G06G 7/12 Arrangements for performing computing operations, e.g. operational amplifiers amplifiers in general H03F; adapted for telemeasuring or for indicating or recording the results of the measurement G01D1/10, G01D1/16; for fuzzy computing G06N7/02
• CPC Class Codes: G06G 7/16 for multiplication or division G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/088 Non-supervised learning, e.g. competitive learning
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0021 Auxiliary circuits
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/15 Current-voltage curve
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Abstract

The invention is notably directed to a device for performing a matrix-vector multiplication of a matrix with a vector. The device comprises a memory crossbar array comprising of row lines, of columns lines and of junctions arranged between the row lines and the column lines. Each junction comprises a programmable resistive memory element. The device comprises a signal generator and a readout circuit. The device is configured to perform a calibration procedure to compensate for conductance variations of the resistive memory elements. The calibration procedure is configured to program a calibration subset of the plurality of resistive memory elements to initial conductance values and to apply a constant calibration voltage to the row lines of the calibration subset. The device is configured to read calibration current values of the column lines of the calibration subset and to derive an estimation of a conductance variation parameter from the calibration current values.

Claims

1. A device for performing a matrix-vector multiplication of a matrix with a vector, the device comprising:

a memory crossbar array comprising

a plurality of row lines;

a plurality of columns lines;

a plurality of junctions arranged between the plurality of row lines and the plurality of column lines, wherein each junction comprises a programmable resistive memory element;

a signal generator configured to

apply programming signals to the resistive memory elements to program conductance values for the matrix-vector multiplication;

a readout circuit configured to

apply read voltages to the row lines of the memory crossbar array;

read out current values of column lines of the memory crossbar array;

wherein

the device is configured to perform a calibration procedure to compensate for conductance variations of the resistive memory elements, the calibration procedure being configured to;

program a calibration subset of the plurality of resistive memory elements to initial conductance values;

apply a constant calibration voltage to the row lines of the calibration subset;

read calibration current values of the column lines of the calibration subset; and

derive an estimation of a conductance variation parameter from the calibration current values.

2. A device according to claim 1, wherein

the conductance values represent matrix values of the matrix of the matrix-vector multiplication;

the read voltages represent vector values of the vector of the matrix-vector multiplication; and

the current values represent result values of vector elements of a product vector of the matrix-vector multiplication.

3. A device according to claim 1, wherein the device is configured to perform the calibration procedure at regular predefined intervals.

4. A device according to claim 1, wherein the plurality of junctions comprises a serial arrangement of a resistive memory element and a transistor.

5. A device according to claim 1, wherein

the device is configured to

compute the sum of the initial conductance values of the resistive memory elements of the calibration subset;

compute the sum of the calibration current values of the column lines of the calibration subset; and

estimate the conductance variation parameter from the ratio of the sum of the calibration current values to the sum of the initial conductance values.

6. A device according to claim 1, wherein the device is configured to

encode the initial conductance values of the subset by a matrix G_0ij;

derive the conductance variation parameter α

as follows;

7. A device according to claim 1, wherein the calibration subset of memory elements comprises less than 20% of the total number of memory elements of the memory array.

8. A device according to claim 1, wherein the calibration subset of memory elements comprises between 1,000 and 20,000 memory elements.

9. A device according to claim 1, wherein the device is configured

to perform multiple runs for the matrix-vector multiplication;

and

to perform an averaging of result values of the multiple runs.

10. A device according to claim 1, wherein the resistive memory elements are one of Phase change memory (PCM) elements, Conductive bridge resistive memory elements, Metal-oxide resistive random access memory (RRAM) elements, Magneto-resistive random access memory (MRAM) elements, Ferroelectric random access memory (FeRAM) elements, optical memory elements, and a system device, the system device comprising transistors, resistors, capacitors, and/or inductors configured to jointly emulate a behavior of a resistive memory element.

11. A device according to claim 10, wherein the resistive memory elements are phase change memory elements and wherein the device is configured to:

apply a Reset-pulse to the phase change memory elements in order to bring the phase change memory elements in the amorphous state;

apply as programming signals current pulses to the phase change memory elements that heat the phase change memory elements above the crystallization temperature, thereby lowering the conductance of the phase change memory elements to a desired conductance value.

12. A device according to claim 1, wherein the signal generator is configured to program the conductance values of the resistive memory elements by an iterative program and verify procedure.

13. A method for calibrating a device for performing a matrix-vector multiplication of a matrix with a vector, the device further comprising:

a memory crossbar array comprising a plurality of row lines, a plurality of columns lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines, wherein each junction comprises a programmable resistive memory element;

a signal generator; and

a readout circuit;

the method comprising performing a calibration procedure comprising

programming a calibration subset of the plurality of resistive memory elements to initial conductance values;

applying a constant calibration voltage to the row lines of the calibration subset;

reading calibration current values of the column lines of the calibration subset; and

deriving an estimation of a conductance variation parameter from the calibration current values.

14. A method as claimed in claim 13, further comprising;

performing the calibration procedure at regular predefined intervals.

15. A method as claimed in claim 13, further comprising:

computing the sum of the initial conductance values of the resistive memory elements of the calibration subset;

computing the sum of the calibration current values of the column lines of the calibration subset; and

estimating the conductance variation parameter from the ratio of the sum of the calibration current values to the sum of the initial conductance values.

16. A method as claimed in claim 13, further comprising:

encoding the initial conductance values of the subset by a matrix G_0ij;

deriving the conductance variation parameter α

as follows;

17. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a device for performing a matrix-vector multiplication of a matrix with a vector, the device comprising;

a memory crossbar array comprising;

a plurality of row lines;

a plurality of columns lines;

a plurality of junctions arranged between the plurality of row lines and the plurality of column lines, wherein each junction comprises a programmable resistive memory element;

a signal generator configured to

apply programming signals to the resistive memory elements to program conductance values for the matrix-vector multiplication;

a readout circuit configured to

apply read voltages to the row lines of the memory crossbar array;

read out current values of column lines of the memory crossbar array;

wherein

the device is configured to perform a calibration procedure to compensate for conductance variations of the resistive memory elements, the calibration procedure being configured to;

program a calibration subset of the plurality of resistive memory elements to initial conductance values;

apply a constant calibration voltage to the row lines of the calibration subset;

read calibration current values of the column lines of the calibration subset; and

derive an estimation of a conductance variation parameter from the calibration current values.

18. A design structure according to claim 17, wherein

the conductance values represent matrix values of the matrix of the matrix-vector multiplication;

the read voltages represent vector values of the vector of the matrix-vector multiplication; and

the current values represent result values of vector elements of a product vector of the matrix-vector multiplication.

19. A design structure according to claim 17, wherein the device is configured to perform the calibration procedure at regular predefined intervals.

20. A design structure according to claim 17, wherein the plurality of junctions comprise a serial arrangement of a resistive memory element and a transistor.