Booster circuit capable of reducing noise in an output voltage generated thereby

• US 10,079,066 B2
• Filed: 11/06/2017
• Issued: 09/18/2018
• Est. Priority Date: 06/29/2016
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Hioka, Takeshi
• Primary Examiner(s): Auduong, Gene
• Application Number:
  US15/804,355
• Publication Number:
  US 20180061500A1
• Time in Patent Office: 316 Days
• Field of Search: 36518909, 36518911, 365226, 327536, 327537, 327540
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

A booster circuit includes a charge pump circuit and a clock processing circuit. The clock processing circuit includes a first transistor of a first conductivity type, a second transistor of a second conductivity type, and a third transistor of a third conductivity type. The first and second transistors are connected in series between a high-voltage node and a low-voltage node, and gates of the first and second transistors are connected to each other. The third transistor is connected in parallel with the first transistor between the high-voltage node and an output terminal of the clock processing circuit that is connected to a node between the first transistor and the second transistor and to the charge pump circuit.

Claims

1. A booster circuit comprising:

a charge pump circuit including a plurality of transistors connected in series, and a plurality of capacitors each of which is connected to a channel electrode of a corresponding one of the transistors; and

a clock processing circuit including

a first transistor of a first conductivity type and a second transistor of a second conductivity type that are connected in series between a high-voltage node and a low-voltage node, gates of the first and second transistors being connected to each other, and

a third transistor of the second conductivity type connected in parallel with the first transistor between the high-voltage node and a first output terminal of the clock processing circuit that is connected to a node between the first transistor and the second transistor and to at least one of the capacitors of the charge pump circuit.

2. The booster circuit according to claim 1, wherein

the clock processing circuit inputs a clock signal to the gates of the first and second transistors, and an inverted clock signal to a gate of the third transistor.

3. The booster circuit according to claim 2, wherein

when the high-voltage terminal is at a voltage level not sufficient to turn on the first transistor, the third transistor is turned on.

4. The booster circuit according to claim 1, wherein

the clock processing circuit inputs an inverted clock signal to the gates of the first and second transistors, and a clock signal to a gate of the third transistor.

5. The booster circuit according to claim 4, wherein

when the high-voltage terminal is at a voltage level not sufficient to turn on the first transistor, the third transistor is turned on.

6. The booster circuit according to claim 1, wherein

the clock processing circuit further includes a fourth transistor of the first conductivity type that is connected to the high-voltage node, and a feedback signal corresponding to the output voltage of the charge pump circuit is applied to a gate of the fourth transistor.

7. The booster circuit according to claim 6, wherein

the clock processing circuit further includes

a fifth transistor of the first conductivity type and a sixth transistor of the second conductivity type that are connected in series between the high-voltage node and the low-voltage node, gates of the fifth and sixth transistors being connected to each other, and

a seventh transistor of the second conductivity type connected in parallel with the fifth transistor between the high-voltage node and a second output terminal of the clock processing circuit that is connected to a node between the fifth transistor and the sixth transistor and to at least one of the capacitors of the charge pump circuit that is different from said at least one of the capacitors connected to the output terminal.

8. The booster circuit according to claim 7, wherein

the clock processing circuit inputs a clock signal to gates of the first, second, and seventh transistors, and an inverted clock signal to gates of the third, fifth, and sixth transistors.

9. The booster circuit according to claim 7, wherein

the clock processing circuit inputs an inverted clock signal to gates of the first, second, and seventh transistors, and a clock signal to gates of the third, fifth, and sixth transistors.

10. The booster circuit according to claim 7, wherein

the clock processing circuit further includes a first inverter having an output terminal that is connected to the gates of the first and second transistors, and a second inverter having an output terminal that is connected to the gates of the fifth and sixth transistors and to an input terminal of the first inverter.

11. A semiconductor memory device comprising:

a semiconductor memory cell array; and

a peripheral circuit configured to control operation of the semiconductor memory cell array, the peripheral circuit including a booster circuit configured to generate voltages used for the operation, wherein

the booster circuit includes;

a charge pump circuit including a plurality of transistors connected in series, and a plurality of capacitors each of which is connected to a channel electrode of a corresponding one of the transistors; and

a clock processing circuit configured to output an output clock signal to at least one of the capacitors of the charge pump circuit based on a clock signal, a first supply voltage and a feedback signal from the charge pump circuit, a voltage of the output clock signal being adjustable to be any value between a ground voltage and the first supply voltage based on the feedback signal.

12. The semiconductor memory device according to claim 11, wherein

the feedback signal corresponds to an output voltage of the charge pump circuit.

13. The semiconductor memory device according to claim 11, wherein the clock processing circuit further includes

a first inverter connected to a first input node, a high voltage node, a first low voltage node, and a first output node, the first output node connected to the one of the capacitors of the charge pump circuit;

a first transistor connected between the high voltage node of the first inverter and a supply voltage node, the first supply voltage supplied to the supply voltage node, and the feedback signal supplied to a gate of the first transistor; and

a second transistor connected between the first output node and the high voltage node.

14. The semiconductor memory device according to claim 13, wherein

a conductivity type of the first transistor is different from a conductivity type of the second transistor.

15. The semiconductor memory device according to claim 13, wherein

the clock processing circuit inputs the clock signal to the first input node of the first inverter, and an inverted clock signal to a gate of the second transistor.

16. The semiconductor memory device according to claim 13, wherein

the clock processing circuit further includes a second inverter connected to a second input node, the supply voltage node, a second low voltage node, and the first input node.

17. The semiconductor memory device according to claim 16, wherein the clock processing circuit further includes

a third inverter connected to a third input node, the high voltage node, a third low voltage node and a second output node connected to one of the capacitors of the charge pump circuit;

and

a third transistor connected between the second output node and the high voltage node.

18. The semiconductor memory device according to claim 17, wherein

the clock processing circuit inputs a clock signal to the first inverter, and an inverted clock signal to the third inverter and a gate of the second transistor.

19. The semiconductor memory device according to claim 17, wherein

a conductivity type of the second transistor is the same as a conductivity type of the third transistor.

20. The semiconductor memory device according to claim 17, wherein

a conductivity type of the second transistor is the same as a conductivity type of the third transistor and different from the first transistor.