Memory cells and memory arrays

• US 10,079,235 B2
• Filed: 07/31/2017
• Issued: 09/18/2018
• Est. Priority Date: 08/31/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Mathew, Suraj J., Singanamalla, Raghunath, Ahmed, Fawad, Brown, Kris K., Nair, Vinay, Yang, Gloria, Simsek-Ege, Fatma Arzum, Tran, Diem Thy N.
• Primary Examiner(s): Cao, Phat X
• Application Number:
  US15/664,183
• Publication Number:
  US 20180061836A1
• Time in Patent Office: 414 Days
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Claims

1. A memory cell comprising:

a three-transistor-one-capacitor (3T-1C) configuration;

the three transistors of the 3T-1C configuration being a first transistor, a second transistor and a third transistor;

a semiconductor pillar extending along the second and third transistors and comprising channel regions and source/drain regions of the second and third transistors;

wherein all of the first, second and third transistors are vertically displaced relative to one another;

wherein the capacitor of the 3T-1C configuration has an inner node, an outer node, and a dielectric material between the inner and outer nodes;

the inner node being electrically coupled with a source/drain region of the first transistor and with a gate of the second transistor;

wherein the first transistor is between the capacitor and a bitline; and

wherein the outer node of the capacitor is against an electrically conductive structure at a common plate voltage, and wherein the semiconductor pillar has an end against said electrically conductive structure.

2. A memory cell comprising:

a three-transistor-one-capacitor (3T-1C) configuration;

the three transistors of the 3T-1C configuration being a first transistor, a second transistor and a third transistor;

a write bitline;

the first transistor being under the write bitline and comprising a first channel region between first and second source/drain regions;

the first source/drain region being electrically coupled with the write bitline;

the first transistor having a first transistor gate along the first channel region;

the capacitor of the 3T-1C configuration being under the first transistor;

the capacitor having an inner node, an outer node, and a capacitor dielectric material between the inner and outer nodes;

the second source/drain region being electrically coupled with the inner node;

the second transistor having a second transistor gate electrically coupled with the inner node and having a second channel region;

the third transistor being under the second transistor and having a third transistor gate along a third channel region;

a semiconductor pillar extending along the second and third gates;

the second and third channel regions being within semiconductor material of the semiconductor pillar;

a read bitline under the third transistor and directly against the semiconductor pillar; and

wherein the second transistor has third and fourth source/drain regions on opposing sides of the second channel region, and the third transistor has fifth and sixth source/drain regions on opposing sides of the third channel region;

wherein the fourth and fifth source/drain regions overlap one another within semiconductor material of the semiconductor pillar;

wherein the outer node of the capacitor contacts an electrically conductive structure at a common plate voltage;

wherein the semiconductor pillar contacts the electrically conductive structure; and

wherein the third source/drain region is within the semiconductor pillar and extends to the electrically conductive structure.

3. The memory cell of claim 2 wherein the sixth source/drain region extends to the read bitline.