Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor
First Claim
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1. A semiconductor memory array comprising:
- a plurality of multi-port semiconductor memory cells arranged in a matrix of rows and columns, wherein each said multi-port semiconductor memory cell comprises;
a plurality of gates;
a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said memory cell;
a plurality of conductive regions of a second conductivity type,wherein adjacent ones of each of said plurality of gates are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions;
a region of a second conductivity type electrically connected to a back bias terminal,wherein applying a voltage to said back bias terminal results in at least two stable common body region charge levels; and
wherein said back bias terminal is commonly connected to at least two of said multi-port semiconductor memory cells.
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Abstract
Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
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Citations
20 Claims
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1. A semiconductor memory array comprising:
a plurality of multi-port semiconductor memory cells arranged in a matrix of rows and columns, wherein each said multi-port semiconductor memory cell comprises; a plurality of gates; a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said memory cell; a plurality of conductive regions of a second conductivity type, wherein adjacent ones of each of said plurality of gates are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions; a region of a second conductivity type electrically connected to a back bias terminal, wherein applying a voltage to said back bias terminal results in at least two stable common body region charge levels; and wherein said back bias terminal is commonly connected to at least two of said multi-port semiconductor memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor memory array comprising:
a plurality of multi-port semiconductor memory cells arranged in a matrix of rows and columns, wherein each said multi-port semiconductor memory cell comprises; a plurality of transistors, each of the plurality of transistors comprising; a common body region configured to store a charge that is indicative of the state of said multi-port semiconductor memory cell; and a plurality of gates, wherein said common body region is shared among the plurality of transistors; a layer beneath said common body region wherein said common body region is positioned between said plurality of gates and said layer; and a back bias terminal connected to said layer and configured to perform at least one of injecting a charge into and extracting the charge out of the common body region to maintain said memory state of the multi-port semiconductor memory cell resulting in at least two stable common body region charge levels, wherein said back bias terminal is commonly connected to at least two of said multi-port semiconductor memory cells. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
Specification