Compact three-dimensional mask-programmed read-only memory

• US 10,079,239 B2
• Filed: 03/10/2017
• Issued: 09/18/2018
• Est. Priority Date: 04/14/2014
• Status: Expired due to Fees

• Current Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): Liu, Xiaoming
• Application Number:
  US15/455,178
• Publication Number:
  US 20170186811A1
• Time in Patent Office: 557 Days
• Field of Search: None
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 17/04 using capacitive elements G11C17/06, G11C17/14 take precedence
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors

Abstract

A compact three-dimensional mask-programmed read-only memory (3D-MPROM_C) is disclosed. Its memory array and a decoding stage thereof are formed on a same memory level above the substrate. The memory layers of the memory devices in the memory array have at least two different thicknesses, while the middle layer of the decoding device in the decoding stage has the same thickness as the thinnest memory layer.

Claims

1. A compact three-dimensional mask-programmed read-only memory (3D-MPROM_C), comprising:

a semiconductor substrate with transistors thereon;

a memory level stacked above said semiconductor substrate, said memory level comprising at least a memory array and at least an above-substrate decoding stage thereof;

at least a contact via coupling said memory level with said semiconductor substrate;

wherein said memory array comprises;

a first address-line extending from said memory array to said above-substrate decoding stage;

a second address-line intersecting said first address-line;

a memory device located at the intersection of said first and second address-lines, said memory device comprising a memory layer between said first and second address-lines, wherein the thickness of said memory layer represents digital information stored in said memory device;

said above-substrate decoding stage comprises;

a control line intersecting said first address-line, wherein said first address-line is physically continuous in said above-substrate decoding stage;

a decoding device located at the intersection of said first address-line and said control line, said decoding device comprising a middle layer between said first address-line and said control line, wherein said decoding device has a conduction mode and a blocking mode;

wherein,

said first address-line is a conductive line except for a semi-conductive portion intersecting said control line;

the memory layers of different memory devices have different thicknesses; and

said middle layer of said decoding device has the same thickness as the thinnest memory layer.

2. The memory according to claim 1, wherein said memory device comprises a diode or a diode-like device.

3. The memory according to claim 1, wherein said memory device is a two-terminal device.

4. The memory according to claim 1, wherein said memory device is a mask-programmed read-only memory (mask-ROM) cell.

5. The memory according to claim 4, wherein said mask-ROM cell stores more than one bit.

6. The memory according to claim 1, wherein said decoding device comprises a transistor or a transistor-like device.

7. The memory according to claim 1, wherein said decoding device is a three-terminal device.

8. The memory according to claim 1, wherein said decoding device comprises a pass-transistor.

9. The memory according to claim 1, wherein said decoding device comprises a MOSFET.

10. The memory according to claim 1, wherein said decoding device is positioned between said memory device and said contact via.

11. A compact three-dimensional mask-programmed read-only memory (3D-MPROM_C), comprising:

a semiconductor substrate with transistors thereon;

a memory level stacked above said semiconductor substrate, said memory level comprising at least a memory array and at least an above-substrate decoding stage thereof;

at least a contact via coupling said memory level with said semiconductor substrate;

wherein said memory array comprises;

an x-line extending from said memory array to said above-substrate decoding stage;

first and second y-lines intersecting said x-line;

a first memory device located at the intersection of said x-line and said first y-line, said first memory device comprising a first memory layer between said x-line and said first y-line;

a second memory device located at the intersection of said x-line and said second y-line, said second memory device comprising a second memory layer between said x-line and said second y-line;

wherein said first memory layer is thinner than said second memory layer;

said above-substrate decoding stage comprises;

a control line (c-line) intersecting said x-line, wherein said x-line is physically continuous in said above-substrate decoding stage;

a decoding device located at the intersection of said x-line and said c-line, said decoding device comprising a middle layer between said x-line and said c-line, wherein said decoding device has a conduction mode and a blocking mode;

wherein,

said x-line is a conductive line except for a semi-conductive portion intersecting said c-line; and

said middle layer in said decoding device has the same thickness as said first memory layer.

12. The memory according to claim 11, wherein said memory device comprises a diode or a diode-like device.

13. The memory according to claim 11, wherein said memory device is a two-terminal device.

14. The memory according to claim 11, wherein said memory device is a mask-programmed read-only memory (mask-ROM) cell.

15. The memory according to claim 14, wherein said mask-ROM cell stores more than one bit.

16. The memory according to claim 11, wherein said decoding device comprises a transistor or a transistor-like device.

17. The memory according to claim 11, wherein said decoding device is a three-terminal device.

18. The memory according to claim 11, wherein said decoding device comprises a pass-transistor.

19. The memory according to claim 11, wherein said decoding device comprises a MOSFET.

20. The memory according to claim 11, wherein said decoding device is positioned between said memory device and said contact via.