Method of integrating a charge-trapping gate stack into a CMOS flow
First Claim
1. An apparatus comprising:
- a substrate having a surface;
a dielectric stack formed on the surface in a first region, the dielectric stack comprising;
a tunneling dielectric formed directly on the surface of the substrate, anda charge-trapping layer formed directly on the tunneling dielectric;
a blocking oxide formed overlying the charge-trapping layer; and
a gate oxide of a field-effect transistor (FET) formed on the surface in a second region, the gate oxide formed simultaneous to the blocking oxide.
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Abstract
A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap layer and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.
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Citations
20 Claims
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1. An apparatus comprising:
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a substrate having a surface; a dielectric stack formed on the surface in a first region, the dielectric stack comprising; a tunneling dielectric formed directly on the surface of the substrate, and a charge-trapping layer formed directly on the tunneling dielectric; a blocking oxide formed overlying the charge-trapping layer; and a gate oxide of a field-effect transistor (FET) formed on the surface in a second region, the gate oxide formed simultaneous to the blocking oxide. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A non-volatile memory device comprising:
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a substrate having a surface; a dielectric stack formed on the surface in a first region, the dielectric stack comprising; a tunneling dielectric formed directly on the surface of the substrate, and a charge-trapping layer formed directly on the tunneling dielectric; a blocking layer formed overlying the charge-trapping layer; a first gate layer formed overlying the blocking layer; a first gate oxide layer of a metal-oxide-semiconductor (MOS) device formed on the surface in a second region, the first gate oxide layer formed simultaneous with the blocking layer; a second gate oxide layer of the MOS device formed on the surface in the second region; a second gate layer formed on the first gate oxide layer; and a third gate layer formed on the second gate oxide layer, wherein the first, second, and third gate layers are formed substantially simultaneously. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A semiconductor device comprising:
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a substrate having a surface; a dielectric stack formed on the surface in a first region, the dielectric stack comprising; a tunneling dielectric formed directly on the surface of the substrate, and a charge-trapping layer formed directly on the tunneling dielectric; a blocking oxide formed overlying the charge-trapping layer; a MOS device disposed on the substrate, the MOS device comprising; a first gate oxide formed on the substrate, the first gate oxide formed simultaneous to the blocking oxide, a first gate formed on the first gate oxide, and a first plurality of spacers formed adjacent to the first gate; and an HV MOS device, the HV MOS device comprising; a second gate oxide formed on the substrate, a second gate formed on the second gate oxide, and a second plurality of spacers formed adjacent to the second gate. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification