×

Method of integrating a charge-trapping gate stack into a CMOS flow

  • US 10,079,243 B2
  • Filed: 10/22/2015
  • Issued: 09/18/2018
  • Est. Priority Date: 02/15/2012
  • Status: Active Grant
First Claim
Patent Images

1. An apparatus comprising:

  • a substrate having a surface;

    a dielectric stack formed on the surface in a first region, the dielectric stack comprising;

    a tunneling dielectric formed directly on the surface of the substrate, anda charge-trapping layer formed directly on the tunneling dielectric;

    a blocking oxide formed overlying the charge-trapping layer; and

    a gate oxide of a field-effect transistor (FET) formed on the surface in a second region, the gate oxide formed simultaneous to the blocking oxide.

View all claims
  • 4 Assignments
Timeline View
Assignment View
    ×
    ×