Semiconductor device and manufacturing method thereof

• US 10,079,251 B2
• Filed: 05/11/2017
• Issued: 09/18/2018
• Est. Priority Date: 11/06/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Miyake, Hiroyuki
• Primary Examiner(s): Ahmadi, Mohsen
• Application Number:
  US15/592,599
• Publication Number:
  US 20170250201A1
• Time in Patent Office: 495 Days
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/13069 Thin film transistor [TFT]

Abstract

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

Claims

1. A semiconductor device comprising:

a transistor comprising;

a first electrode layer;

a first insulating film over the first electrode layer;

an oxide semiconductor layer over the first insulating film;

a second electrode layer on the oxide semiconductor layer, the second electrode layer having a first end portion overlapping with the first electrode layer;

a third electrode layer on the oxide semiconductor layer, the third electrode layer having a second end portion overlapping with the first electrode layer;

a second insulating film in contact with the second electrode layer, the third electrode layer, and the oxide semiconductor layer; and

a fourth electrode layer over the first electrode layer with at least the oxide semiconductor layer and the second insulating film interposed between the fourth electrode layer and the first electrode layer,

wherein the first electrode layer has an edge portion overlapping with the oxide semiconductor layer,

wherein the oxide semiconductor layer has an edge portion overlapping with the first electrode layer, and

wherein the fourth electrode layer is in electrical contact with the second electrode layer in a region in which the first electrode layer overlaps the second electrode layer.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, zinc, and one or more metal elements selected from gallium, aluminum, manganese, cobalt and tin.

3. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer comprises:

a first region comprising crystals; and

a second region comprising an amorphous region or a mixture region of amorphousness and microcrystals.

4. The semiconductor device according to claim 1, wherein an energy gap of the oxide semiconductor is greater than or equal to 2 eV.

5. A display device comprising:

a driver circuit comprising the semiconductor device according to claim 1.

6. A semiconductor device comprising:

a first transistor over a substrate; and

a second transistor over the substrate, the first transistor and the second transistor each comprising;

a first electrode layer;

a first insulating film over the first electrode layer;

an oxide semiconductor layer over the first insulating film;

a second electrode layer on the oxide semiconductor layer, the second electrode layer having a first end portion overlapping with the first electrode layer;

a third electrode layer on the oxide semiconductor layer, the third electrode layer having a second end portion overlapping with the first electrode layer;

a second insulating film in contact with the second electrode layer, the third electrode layer and the oxide semiconductor layer; and

a fourth electrode layer over the first electrode layer with at least the oxide semiconductor layer and the second insulating film interposed between the fourth electrode layer and the first electrode layer,

wherein the third electrode layer of the first transistor is electrically connected to the second electrode layer of the second transistor,

wherein the first electrode layer of the second transistor has an edge portion overlapping with the oxide semiconductor layer of the second transistor,

wherein the oxide semiconductor layer of the second transistor has an edge portion overlapping with the first electrode layer of the second transistor, and

wherein the fourth electrode layer of the second transistor is in electrical contact with the second electrode layer of the second transistor in a region in which the first electrode layer of the second transistor overlaps the second electrode layer of the second transistor.

7. The semiconductor device according to claim 6, wherein the oxide semiconductor layer of the first transistor and the oxide semiconductor layer of the second transistor each comprise indium, zinc, and one or more metal elements selected from gallium, aluminum, manganese, cobalt and tin.

8. The semiconductor device according to claim 6,

wherein the oxide semiconductor layer of the first transistor and the oxide semiconductor layer of the second transistor each comprise:

a first region comprising crystals; and

a second region comprising an amorphous region or a mixture region of amorphousness and microcrystals.

9. The semiconductor device according to claim 6, wherein the oxide semiconductor layer of the first transistor and the oxide semiconductor layer of the second transistor each comprise an oxide semiconductor whose energy gap is greater than or equal to 2 eV.

10. An inverter circuit comprising the semiconductor device according to claim 6, wherein the first transistor is a depletion transistor and the second transistor is an enhancement transistor.

11. A display device comprising:

a driver circuit comprising the semiconductor device according to claim 6.

12. A display device comprising the semiconductor device according to claim 6, wherein the display device includes a pixel portion and a driver circuit portion which drives the pixel portion.