Memory device comprising an electrically floating body transistor and methods of using

• US 10,079,301 B2
• Filed: 10/30/2017
• Issued: 09/18/2018
• Est. Priority Date: 11/01/2016
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Han, Jin-Woo, Maheshwari, Dinesh, Widjaja, Yuniarto
• Primary Examiner(s): SHOOK, DANIEL P
• Application Number:
  US15/798,342
• Publication Number:
  US 20180122943A1
• Time in Patent Office: 323 Days
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Claims

1. A semiconductor memory cell comprising:

a memory transistor comprising a bi-stable floating body transistor having a first floating body region and a back-bias region configured to generate impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states; and

an access device;

wherein said access device comprises a second floating body region; and

wherein said bi-stable floating body transistor and said access device are electrically connected in series.

2. The semiconductor memory cell of claim 1, wherein a capacitance of said first floating body region is different from a capacitance of said second floating body region.

3. The semiconductor memory cell of claim 1, wherein said memory transistor further comprises a first gate region, and said access device further comprises a second gate region.

4. The semiconductor memory cell of claim 3, wherein a length of the first gate region is less than a length of the second gate region.

5. The semiconductor memory cell of claim 3, wherein a length of the first gate region is greater than a length of the second gate region.

6. The semiconductor memory cell of claim 3, wherein a capacitance of the first gate region is different from a capacitance of the second gate region.

7. The semiconductor memory cell of claim 1, wherein a volume of the first floating body region is smaller than a volume of the second floating body region.

8. The semiconductor memory cell of claim 1, further comprising at least one dummy gate region between said memory transistor and said access device.

9. The semiconductor memory cell of claim 8, wherein said memory transistor comprises a first gate region;

and

wherein a work function of said dummy gate region is higher than a work function of said first gate region.

10. The semiconductor memory cell of claim 1, wherein said semiconductor memory cell is a multi-port memory cell.

11. The semiconductor memory cell of claim 1 comprising a fin structure.

12. A semiconductor memory cell comprising:

a first transistor having a first floating body;

a second transistor having a second floating body;

a buried layer underlying both of said first and second floating bodies;

a first source line region contacting said first floating body;

a first drain region separated from said first source line region and contacting said first floating body;

a first gate insulated from said first floating body;

an insulating member insulating said first floating body from said second floating body;

a second source line region contacting said second floating body;

a second drain region separated from said second source line region and contacting said second floating body; and

a second gate insulated from said second floating body;

wherein said first drain region is electrically connected to said second source line region; and

wherein a capacitance of said first floating body is different from a capacitance of said second floating body.

13. The semiconductor memory cell of claim 12, wherein a volume of said first floating body is less than a volume of said second floating body.

14. The semiconductor memory cell of claim 12, wherein a length of said first gate is less than a length of said second gate.

15. The semiconductor memory cell of claim 12, wherein a length of said first gate is greater than a length of said second gate.

16. The semiconductor memory cell of claim 12, further comprising at least one dummy gate region between said first transistor and said second transistor.

17. The semiconductor memory cell of claim 16, wherein a work function of said dummy gate region is greater than a work function of said first gate.

18. The semiconductor memory cell of claim 12, wherein said first transistor and said second transistor have the same conductivity type.

19. The semiconductor memory cell of claim 12, wherein said semiconductor memory cell is a multi-port memory cell.

20. The semiconductor memory cell of claim 12 comprising a fin structure.