Vertically aligned carbon nanotube trapezoid FIN structure

• US 10,079,354 B2
• Filed: 04/05/2017
• Issued: 09/18/2018
• Est. Priority Date: 03/31/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cao, Qing, Cheng, Kangguo, Li, Zhengwen, Liu, Fei, Zhang, Zhen
• Primary Examiner(s): Pert, Evan
• Application Number:
  US15/479,468
• Publication Number:
  US 20170207404A1
• Time in Patent Office: 531 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H10K 10/464 Lateral top-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/472 the gate dielectric comprising only inorganic materials
• CPC Class Codes: H10K 10/481 characterised by the gate conductors
• CPC Class Codes: H10K 10/484 characterised by the channel regions
• CPC Class Codes: H10K 10/488 the channel region comprising a layer of composite material having interpenetrating or embedded materials, e.g. a mixture of donor and acceptor moieties, that form a bulk heterojunction
• CPC Class Codes: H10K 10/491 Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
• CPC Class Codes: H10K 10/84 Ohmic electrodes, e.g. source or drain electrodes
• CPC Class Codes: H10K 19/10 comprising field-effect transistors
• CPC Class Codes: H10K 2102/00 Constructional details relating to the organic devices covered by this subclass
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs
• CPC Class Codes: Y10S 977/842 for carbon nanotubes or fullerenes
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

A transistor device includes an array of fin structures arranged on a substrate, each of the fin structures being vertically alternating stacks of a first isoelectric point material having a first isoelectric point and a second isoelectric point material having a second isoelectric point that is different than the first isoelectric point; one or more carbon nanotubes (CNTs) suspended between the fin structures and contacting a side surface of the second isoelectric point material in the fin structures; a gate wrapped around the array of CNTs; and source and drain contacts arranged over the fin structures; wherein each of the fin structures have a trapezoid shape or parallel sides that are oriented about 90° with respect to the substrate.

Claims

1. A method of making a transistor device, the method comprising:

forming an array of fin structures, the array of fin structures being arranged on a substrate and each having a pair of layers, the pair of layers comprising a first isoelectric point material having a first isoelectric point and a second isoelectric point material having a second isoelectric point that is different than the first isoelectric point;

wrapping a gate around carbon nanotubes (CNTs) between the fin structures to suspend the CNTs in the gate, the CNTs contacting a side surface of the second isoelectric point material in the fin structures; and

forming source and drain contacts over the fin structures;

wherein the CNTs are arranged in a non-vertical tapered array within the gate.

2. The method of claim 1, wherein a gate dielectric material surrounds the CNTs and is hafnium oxide.

3. The method of claim 1, wherein a gate dielectric material surrounds the CNTs and is aluminum oxide.

4. The method of claim 1, wherein the CNTs are anchored in the source and drain contacts.

5. The method of claim 1, wherein the gate comprises a metal gate material separated from the source and drain contacts by a gate spacer.

6. The method of claim 1, wherein the gate comprises a metal gate material separated from the source and drain contacts by a gate dielectric material.

7. The method of claim 1, wherein each of the fin structures have a width that is less than a length of the fin structure.

8. The method of claim 1, wherein the CNTs contact the second isoelectric point material by an electrostatic interaction.

9. The method of claim 1, further comprising a positively charged surface monolayer selectively assembled on the second dielectric point material.

10. The method of claim 1, wherein the CNTs are substantially parallel to the substrate.

11. A method of making a transistor device, the method comprising:

forming a fin structure, the fin structure comprising at least one pair of layers, each pair of layers comprising a first isoelectric point material having a first isoelectric point and a second isoelectric point material having a second isoelectric point that is different than the first isoelectric point;

selectively contacting carbon nanotubes (CNTs) to a side surface of the second isoelectric point material in the fin structure;

forming source and drain contacts on opposing ends of the fin structure;

removing portions of the fin structure between the source and drain contacts so as to suspend the CNTs in a non-vertical tapered array; and

forming a gate wrapped around the CNTs.

12. The method of claim 11, wherein the fin structure has a trapezoid shape.

13. The method of claim 11, further comprising solubilizing the CNTs with a surfactant before selectively contacting the CNTs to the second isoelectric point material.

14. The method of claim 13, wherein the surfactant is negatively charged.

15. The method of claim 11, wherein the CNTs are substantially parallel to the substrate.

16. The method of claim 11, wherein a gate dielectric material surrounds the CNTs and is hafnium oxide.

17. The method of claim 11, wherein a gate dielectric material surrounds the CNTs and is aluminum oxide.

18. The method of claim 11, wherein the CNTs are anchored in the source and drain contacts.

19. The method of claim 11, wherein the gate comprises a metal gate material separated from the source and drain contacts by a gate spacer.

20. The method of claim 11, wherein the gate comprises a metal gate material separated from the source and drain contacts by a gate dielectric material.