DC offset calibration of wireless receivers

• US 10,079,647 B2
• Filed: 12/10/2014
• Issued: 09/18/2018
• Est. Priority Date: 12/10/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Waheed, Khurram
• Primary Examiner(s): Liu, Shuwang
• Assistant Examiner(s): Ahn, Sung
• Application Number:
  US14/565,745
• Publication Number:
  US 20160173048A1
• Time in Patent Office: 1,378 Days
• CPC Class Codes: H03G 3/001 Digital control of analog signals
• CPC Class Codes: H03G 3/3078 Circuits generating control signals for digitally modulated signals
• CPC Class Codes: H04B 17/21 for calibration; for correcting measurements

Abstract

A receiver system includes an automatic gain control (AGC) module configured to control a first gain control signal to a first gain element having variable gain control. The receiver system also includes a DC (direct current) offset correction block coupled to the AGC module, the DC offset correction block configured to trigger the AGC module to output a set of calibration gain control signals to the first gain element and capture a set of DC offset measurements of a first signal received at the DC offset correction block, where the first signal is passed by the first gain element. The DC offset correction block is further configured to estimate one or more DC offset components using the set of DC offset measurements, and calculate a first correction control signal corresponding to a first gain level of the first gain element using the one or more DC offset components.

Claims

1. A receiver system comprising:

an automatic gain control (AGC) circuitry configured to

control a first gain control signal to a first gain element having variable gain control;

control a second gain control signal to a second gain element having variable gain control;

a DC (direct current) offset correction circuitry coupled to the AGC circuitry, the DC offset correction circuitry configured to

trigger the AGC circuitry to output a set of calibration gain control signals to the first and second gain elements;

capture a set of DC offset measurements of a first signal received at the DC offset correction circuitry, wherein the first signal is passed by the first and second gain elements;

estimate DC offset components using the set of DC offset measurements, the DC offset components including a first DC offset component that is a function of low noise amplifier gain and baseband filter gain, a second DC offset component that is a function of the baseband filter gain without the low noise amplifier gain, and a third DC offset component that is a function of the baseband filter offset and analog to digital converter offset;

calculate a first correction control signal corresponding to a first gain level of the first gain element using the DC offset components;

calculate a second correction control signal corresponding to the first gain level of the second gain element using the DC offset components.

2. The receiver system of claim 1, further comprising:

a first digital-to-analog converter (DAC), wherein

the DC offset correction circuitry is further configured to output one of the correction calibration signals to the first DAC,

the first DAC is configured to output a first DC offset correction signal to the first gain element, and

the first DC offset correction signal is configured to correct one or more of the DC offset components.

3. The receiver system of claim 2, further comprising:

a second DAC, wherein

the DC offset correction block is further configured to output another one of the correction calibration signals to the second DAC,

the second DAC is configured to output a second DC offset correction signal to the second gain element, and

the second DC offset correction signal is configured to correct a residual remaining from the first DC offset correction signal and the DC offset components.

4. The receiver system of claim 2, wherein

the first DAC is configured to map the one of the correction calibration signals to the first DC offset correction signal having an analog component, wherein

the first DAC exhibits a DAC gain term representing a translation from a digital representation of the DC offset correction signal to the analog component.

5. The receiver system of claim 2, wherein

the AGC circuitry is further configured to

control a second gain control signal to a second gain element having variable gain control,

the first signal is further passed by the second gain element, and

the DC offset correction circuitry further configured to

trigger the AGC circuitry to output the set of calibration gain control signals to the second gain element.

6. The receiver system of claim 1, wherein

the AGC circuitry is further configured to

set the first gain control signal to a first value and the second gain control signal to a second value for a time period, and

the DC offset correction circuitry is configured to capture one of the set of DC offset measurements during the time period.

7. The receiver system of claim 1, wherein

the set of DC offset measurements includes a number of measurements that is based on a number of DC offset components exhibited in the receiver system, and

the number of DC offset components is based on a number of gain elements in the receiver system.

8. The receiver system of claim 1, wherein

each DC offset component scales with a cascade of gains exhibited by successive gain elements that pass the first signal, and

the successive gain elements are located in the receiver system before an input of the DC offset correction block.

9. The receiver system of claim 1, wherein

the DC offset correction circuitry is further configured to

store each of the plurality of correction calibration signals and a corresponding gain level in a respective entry of a lookup table, and

the correction calibration signals are selected from the lookup table as a function of a current gain setting of the first gain element.

10. The receiver system of claim 1, further comprising

an analog-to-digital converter (ADC) configured to map an output of the second gain element to a digital representation having a slope, wherein

the slope corresponds to an ADC gain term representing a translation from a voltage of the output of the second gain element to the digital representation.

11. The receiver system of claim 1, wherein

the first signal is one of an in-phase signal and a quadrature signal, and

the first gain element is part of an RF (radio frequency) down-conversion stage.

12. The receiver system of claim 1, wherein

the second gain element is at least one of an in-phase amplifier and a quadrature amplifier.

13. The receiver system of claim 1, wherein

the DC offset correction circuitry is further configured to

calculate a plurality of correction control signals corresponding to a plurality of gain levels of the first gain element using the DC offset components.

14. A semiconductor device comprising:

a receiver system including;

a first gain element;

a second gain element; and

a DC (direct current) offset correction circuitry configured to

capture a set of DC offset measurements of a first signal received at the DC offset correction circuitry, wherein

the first signal is passed by the first and second gain elements;

estimate DC offset components using the set of DC offset measurements, wherein

a first DC offset component is estimated based on a difference between high and low low noise amplifier gain and low baseband filter gain,

a second DC offset component is estimated based on a difference between high baseband filter gain and the low baseband filter gain, and the low low noise amplifier gain, and

a third DC offset component is estimated based on the baseband filter offset and analog to digital converter offset; and

calculate correction calibration signals corresponding to a first gain level of the first gain element using the DC offset components.

15. A method of operating a receiver system comprising:

triggering an automatic gain control (AGC) circuitry of the receiver system to output a set of calibration gain control signals to gain elements having variable gain control;

capturing a set of DC offset measurements of a first signal, wherein the first signal is passed by the gain elements;

estimating DC offset components using the set of DC offset measurements based on a difference between high and low low noise amplifier gains, and low baseband filter gain for a first of the DC offset components, low low noise amplifier gain and a difference between high and low baseband filter gains for a second of the DC offset components, and baseband filter offset and analog to digital converter offset for a third of the DC offset components; and

calculating correction calibration signals over a range of gain levels of the gain elements using the DC offset components.

16. The method of claim 15, further comprising:

setting, by the AGC circuitry, a respective gain control signal of each of the gain elements according to a subset of the set of calibration values for a time period, wherein

one of the set of DC offset measurements is captured during the time period.

17. The method of claim 15, further comprising:

outputting respective ones of the correction calibration signals to first and second digital-to-analog converters (DACs), wherein

each of the DACs is configured to output a DC offset correction signal to one of the gain elements, and

each DC offset correction signal corresponds to one of the correction calibration signals.

18. The method of claim 17, wherein

a combination of each DC offset correction signal output by the first and second DACs is configured to correct the DC offset components.

19. The method of claim 15, further comprising:

storing each of the one or more correction calibration signals and a corresponding one of the one or more gain levels in a respective entry of a lookup table; and

selecting one of the one or more correction calibration signals from the lookup table as a function of a current gain setting of each of the gain elements.